Mike Frysinger fa8f87e53b sim: trace: add a basic cpu register class ...

The bfin/msp430 ports already had trace logic set up for reading/writing
cpu registers, albeit using different unrelated levels (core & vpu).  Add
a proper register class for these and for other ports.

2015-06-24 10:40:17 -04:00

..

bfroms

…

aclocal.m4

sim: rename tconfig.in to tconfig.h

2015-03-16 01:23:52 -04:00

bfin-sim.c

sim: trace: add common macros for logging info

2015-06-12 06:34:20 -04:00

bfin-sim.h

sim: trace: add common macros for logging info

2015-06-12 06:34:20 -04:00

ChangeLog

sim: trace: add a basic cpu register class

2015-06-24 10:40:17 -04:00

config.in

sim: update zlib handling

2015-04-01 01:07:57 -04:00

configure

sim: use AS_HELP_STRING everywhere

2015-06-23 15:02:08 -04:00

configure.ac

sim: dv-sockser: move build to common dir

2015-03-23 04:40:07 -04:00

devices.c

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2015-01-01 13:32:14 +04:00

devices.h

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2015-01-01 13:32:14 +04:00

dv-bfin_cec.c

sim: trace: add common macros for logging info

2015-06-12 06:34:20 -04:00

dv-bfin_cec.h

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dv-bfin_ctimer.c

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dv-bfin_ctimer.h

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dv-bfin_dma.c

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dv-bfin_dma.h

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dv-bfin_dmac.c

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dv-bfin_dmac.h

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dv-bfin_ebiu_amc.c

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dv-bfin_ebiu_amc.h

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dv-bfin_ebiu_ddrc.c

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dv-bfin_ebiu_ddrc.h

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dv-bfin_ebiu_sdc.c

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dv-bfin_ebiu_sdc.h

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dv-bfin_emac.c

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dv-bfin_emac.h

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dv-bfin_eppi.c

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dv-bfin_eppi.h

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dv-bfin_evt.c

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dv-bfin_evt.h

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dv-bfin_gpio2.c

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dv-bfin_gpio2.h

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dv-bfin_gpio.c

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dv-bfin_gpio.h

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dv-bfin_gptimer.c

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dv-bfin_gptimer.h

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dv-bfin_jtag.c

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dv-bfin_jtag.h

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dv-bfin_mmu.c

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dv-bfin_mmu.h

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dv-bfin_nfc.c

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dv-bfin_nfc.h

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dv-bfin_otp.c

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dv-bfin_otp.h

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dv-bfin_pfmon.c

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dv-bfin_pfmon.h

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dv-bfin_pint.c

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dv-bfin_pint.h

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dv-bfin_pll.c

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dv-bfin_pll.h

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dv-bfin_ppi.c

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dv-bfin_ppi.h

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dv-bfin_rtc.c

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dv-bfin_rtc.h

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dv-bfin_sic.c

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dv-bfin_sic.h

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dv-bfin_spi.c

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dv-bfin_spi.h

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dv-bfin_trace.c

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dv-bfin_trace.h

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dv-bfin_twi.c

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dv-bfin_twi.h

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dv-bfin_uart2.c

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dv-bfin_uart2.h

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dv-bfin_uart.c

sim: dv-sockser: add stub funcs when not available

2015-03-23 04:14:27 -04:00

dv-bfin_uart.h

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dv-bfin_wdog.c

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dv-bfin_wdog.h

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dv-bfin_wp.c

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dv-bfin_wp.h

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dv-eth_phy.c

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gui.c

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gui.h

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insn_list.def

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interp.c

sim: trace: add a basic cpu register class

2015-06-24 10:40:17 -04:00

linux-fixed-code.h

…

linux-fixed-code.s

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linux-targ-map.h

sim: callback: add human readable strings for debugging to maps

2015-06-17 13:19:51 -04:00

machs.c

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machs.h

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Makefile.in

sim: unify sim-cpu usage

2015-04-15 02:19:52 -04:00

proc_list.def

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2015-01-01 13:32:14 +04:00

sim-main.h

sim: trace: add a basic cpu register class

2015-06-24 10:40:17 -04:00

tconfig.h

sim: rename tconfig.in to tconfig.h

2015-03-16 01:23:52 -04:00

TODO

sim: bfin: add flush/HWERR todo

2013-06-17 04:43:22 +00:00