1206 lines
20 KiB
Plaintext
1206 lines
20 KiB
Plaintext
:option:::insn-bit-size:16
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:option:::hi-bit-nr:15
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:option:::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
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:option:::format-names:XI,XII,XIII
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:option:::format-names:XIV,XV
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:option:::format-names:Z
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:model:::v850:v850:
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:option:::multi-sim:true
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:model:::v850e:v850e:
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:option:::multi-sim:true
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:model:::v850e1:v850e1:
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// Cache macros
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:cache:::unsigned:reg1:RRRRR:(RRRRR)
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:cache:::unsigned:reg2:rrrrr:(rrrrr)
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:cache:::unsigned:reg3:wwwww:(wwwww)
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:cache:::unsigned:disp4:dddd:(dddd)
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:cache:::unsigned:disp5:dddd:(dddd << 1)
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:cache:::unsigned:disp7:ddddddd:ddddddd
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:cache:::unsigned:disp8:ddddddd:(ddddddd << 1)
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:cache:::unsigned:disp8:dddddd:(dddddd << 2)
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:cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
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:cache:::unsigned:disp16:dddddddddddddddd:EXTEND16 (dddddddddddddddd)
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:cache:::unsigned:disp16:ddddddddddddddd: EXTEND16 (ddddddddddddddd << 1)
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:cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 22 - 1)
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:cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
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:cache:::unsigned:imm6:iiiiii:iiiiii
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:cache:::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
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:cache:::unsigned:imm5:iiii:(32 - (iiii << 1))
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:cache:::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
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:cache:::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
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:cache:::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
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:cache:::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
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:cache:::unsigned:vector:iiiii:iiiii
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:cache:::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
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:cache:::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
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:cache:::unsigned:bit3:bbb:bbb
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// What do we do with an illegal instruction?
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:internal::::illegal:
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{
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sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
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(unsigned long) cia);
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sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
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}
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// Add
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rrrrr,001110,RRRRR:I:::add
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"add r<reg1>, r<reg2>"
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{
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COMPAT_1 (OP_1C0 ());
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}
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rrrrr,010010,iiiii:II:::add
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"add <imm5>,r<reg2>"
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{
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COMPAT_1 (OP_240 ());
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}
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// ADDI
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rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
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"addi <simm16>, r<reg1>, r<reg2>"
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{
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COMPAT_2 (OP_600 ());
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}
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// AND
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rrrrr,001010,RRRRR:I:::and
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"and r<reg1>, r<reg2>"
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{
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COMPAT_1 (OP_140 ());
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}
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// ANDI
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rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
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"andi <uimm16>, r<reg1>, r<reg2>"
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{
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COMPAT_2 (OP_6C0 ());
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}
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// Map condition code to a string
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:%s::::cccc:int cccc
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{
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switch (cccc)
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{
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case 0xf: return "gt";
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case 0xe: return "ge";
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case 0x6: return "lt";
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case 0x7: return "le";
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case 0xb: return "h";
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case 0x9: return "nl";
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case 0x1: return "l";
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case 0x3: return "nh";
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case 0x2: return "e";
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case 0xa: return "ne";
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case 0x0: return "v";
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case 0x8: return "nv";
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case 0x4: return "n";
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case 0xc: return "p";
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/* case 0x1: return "c"; */
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/* case 0x9: return "nc"; */
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/* case 0x2: return "z"; */
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/* case 0xa: return "nz"; */
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case 0x5: return "r"; /* always */
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case 0xd: return "sa";
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}
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return "(null)";
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}
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// Bcond
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ddddd,1011,ddd,cccc:III:::Bcond
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"b%s<cccc> <disp9>"
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{
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int cond;
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if ((ddddd == 0x00) && (ddd == 0x00) && (cccc == 0x05)) {
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// Special case - treat "br *" like illegal instruction
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sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
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} else {
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cond = condition_met (cccc);
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if (cond)
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nia = cia + disp9;
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TRACE_BRANCH1 (cond);
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}
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}
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// BSH
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rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
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*v850e
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*v850e1
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"bsh r<reg2>, r<reg3>"
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{
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unsigned32 value;
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TRACE_ALU_INPUT1 (GR[reg2]);
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value = (MOVED32 (GR[reg2], 23, 16, 31, 24)
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| MOVED32 (GR[reg2], 31, 24, 23, 16)
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| MOVED32 (GR[reg2], 7, 0, 15, 8)
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| MOVED32 (GR[reg2], 15, 8, 7, 0));
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GR[reg3] = value;
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PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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if (value == 0) PSW |= PSW_Z;
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if (value & 0x80000000) PSW |= PSW_S;
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if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY;
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TRACE_ALU_RESULT (GR[reg3]);
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}
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// BSW
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rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
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*v850e
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*v850e1
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"bsw r<reg2>, r<reg3>"
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{
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#define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
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unsigned32 value;
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TRACE_ALU_INPUT1 (GR[reg2]);
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value = GR[reg2];
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value >>= 24;
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value |= (GR[reg2] << 24);
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value |= ((GR[reg2] << 8) & 0x00ff0000);
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value |= ((GR[reg2] >> 8) & 0x0000ff00);
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GR[reg3] = value;
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PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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if (value == 0) PSW |= PSW_Z;
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if (value & 0x80000000) PSW |= PSW_S;
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if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
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TRACE_ALU_RESULT (GR[reg3]);
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}
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// CALLT
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0000001000,iiiiii:II:::callt
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*v850e
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*v850e1
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"callt <imm6>"
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{
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unsigned32 adr;
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unsigned32 off;
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CTPC = cia + 2;
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CTPSW = PSW;
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adr = (CTBP & ~1) + (imm6 << 1);
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off = load_mem (adr, 2) & ~1; /* Force alignment */
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nia = (CTBP & ~1) + off;
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TRACE_BRANCH3 (adr, CTBP, off);
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}
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// CLR1
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10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
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"clr1 <bit3>, <disp16>[r<reg1>]"
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{
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COMPAT_2 (OP_87C0 ());
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}
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rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
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*v850e
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*v850e1
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"clr1 r<reg2>, [r<reg1>]"
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{
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COMPAT_2 (OP_E407E0 ());
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}
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// CTRET
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0000011111100000 + 0000000101000100:X:::ctret
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*v850e
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*v850e1
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"ctret"
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{
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nia = (CTPC & ~1);
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PSW = (CTPSW & (CPU)->psw_mask);
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TRACE_BRANCH1 (PSW);
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}
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// CMOV
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rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
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*v850e
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*v850e1
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"cmov %s<cccc>, r<reg1>, r<reg2>, r<reg3>"
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{
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int cond = condition_met (cccc);
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TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]);
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GR[reg3] = cond ? GR[reg1] : GR[reg2];
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TRACE_ALU_RESULT (GR[reg3]);
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}
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rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
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*v850e
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*v850e1
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"cmov %s<cccc>, <imm5>, r<reg2>, r<reg3>"
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{
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int cond = condition_met (cccc);
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TRACE_ALU_INPUT3 (cond, imm5, GR[reg2]);
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GR[reg3] = cond ? imm5 : GR[reg2];
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TRACE_ALU_RESULT (GR[reg3]);
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}
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// CMP
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rrrrr,001111,RRRRR:I:::cmp
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"cmp r<reg1>, r<reg2>"
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{
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COMPAT_1 (OP_1E0 ());
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}
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rrrrr,010011,iiiii:II:::cmp
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"cmp <imm5>, r<reg2>"
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{
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COMPAT_1 (OP_260 ());
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}
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// DI
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0000011111100000 + 0000000101100000:X:::di
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"di"
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{
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COMPAT_2 (OP_16007E0 ());
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}
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// DISPOSE
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// 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
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// "dispose <imm5>, <list12>"
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0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
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*v850e
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*v850e1
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"dispose <imm5>, <list12>":RRRRR == 0
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"dispose <imm5>, <list12>, [reg1]"
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{
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int i;
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SAVE_2;
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trace_input ("dispose", OP_PUSHPOP1, 0);
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SP += (OP[3] & 0x3e) << 1;
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/* Load the registers with lower number registers being retrieved
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from higher addresses. */
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for (i = 12; i--;)
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if ((OP[3] & (1 << type1_regs[ i ])))
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{
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State.regs[ 20 + i ] = load_mem (SP, 4);
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SP += 4;
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}
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if ((OP[3] & 0x1f0000) != 0)
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{
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nia = State.regs[ (OP[3] >> 16) & 0x1f];
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}
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trace_output (OP_PUSHPOP1);
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}
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// DIV
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rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
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*v850e
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*v850e1
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"div r<reg1>, r<reg2>, r<reg3>"
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{
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COMPAT_2 (OP_2C007E0 ());
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}
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// DIVH
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rrrrr!0,000010,RRRRR!0:I:::divh
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"divh r<reg1>, r<reg2>"
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{
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unsigned32 ov, s, z;
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signed long int op0, op1, result;
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trace_input ("divh", OP_REG_REG, 0);
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PC = cia;
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OP[0] = instruction_0 & 0x1f;
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OP[1] = (instruction_0 >> 11) & 0x1f;
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/* Compute the result. */
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op0 = EXTEND16 (State.regs[OP[0]]);
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op1 = State.regs[OP[1]];
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if (op0 == 0xffffffff && op1 == 0x80000000)
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{
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result = 0x80000000;
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ov = 1;
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}
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else if (op0 != 0)
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{
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result = op1 / op0;
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ov = 0;
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}
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else
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{
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result = 0x0;
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ov = 1;
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}
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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/* Store the result and condition codes. */
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State.regs[OP[1]] = result;
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PSW &= ~(PSW_Z | PSW_S | PSW_OV);
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PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (ov ? PSW_OV : 0));
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trace_output (OP_REG_REG);
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PC += 2;
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nia = PC;
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}
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rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
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*v850e
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*v850e1
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"divh r<reg1>, r<reg2>, r<reg3>"
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{
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COMPAT_2 (OP_28007E0 ());
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}
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// DIVHU
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rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
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*v850e
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*v850e1
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"divhu r<reg1>, r<reg2>, r<reg3>"
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{
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COMPAT_2 (OP_28207E0 ());
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}
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// DIVU
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rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
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*v850e
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*v850e1
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"divu r<reg1>, r<reg2>, r<reg3>"
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{
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COMPAT_2 (OP_2C207E0 ());
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}
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// EI
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1000011111100000 + 0000000101100000:X:::ei
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"ei"
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{
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COMPAT_2 (OP_16087E0 ());
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}
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// HALT
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0000011111100000 + 0000000100100000:X:::halt
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"halt"
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{
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COMPAT_2 (OP_12007E0 ());
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}
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// HSW
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rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
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*v850e
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*v850e1
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"hsw r<reg2>, r<reg3>"
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{
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unsigned32 value;
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TRACE_ALU_INPUT1 (GR[reg2]);
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value = GR[reg2];
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value >>= 16;
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value |= (GR[reg2] << 16);
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GR[reg3] = value;
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PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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if (value == 0) PSW |= PSW_Z;
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if (value & 0x80000000) PSW |= PSW_S;
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if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
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TRACE_ALU_RESULT (GR[reg3]);
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}
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// JARL
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rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
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"jarl <disp22>, r<reg2>"
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{
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GR[reg2] = nia;
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nia = cia + disp22;
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TRACE_BRANCH1 (GR[reg2]);
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}
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// JMP
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00000000011,RRRRR:I:::jmp
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"jmp [r<reg1>]"
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{
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nia = GR[reg1] & ~1;
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TRACE_BRANCH0 ();
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}
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// JR
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0000011110,dddddd + ddddddddddddddd,0:V:::jr
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"jr <disp22>"
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{
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nia = cia + disp22;
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TRACE_BRANCH0 ();
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}
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// LD
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rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
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"ld.b <disp16>[r<reg1>], r<reg2>"
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{
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COMPAT_2 (OP_700 ());
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}
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rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
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"ld.h <disp16>[r<reg1>], r<reg2>"
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{
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COMPAT_2 (OP_720 ());
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}
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rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
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"ld.w <disp16>[r<reg1>], r<reg2>"
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{
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COMPAT_2 (OP_10720 ());
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}
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rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
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*v850e
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*v850e1
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"ld.bu <disp16>[r<reg1>], r<reg2>"
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{
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COMPAT_2 (OP_10780 ());
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}
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rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
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*v850e
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*v850e1
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"ld.hu <disp16>[r<reg1>], r<reg2>"
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{
|
|
COMPAT_2 (OP_107E0 ());
|
|
}
|
|
|
|
|
|
// LDSR
|
|
regID,111111,RRRRR + 0000000000100000:IX:::ldsr
|
|
"ldsr r<reg1>, s<regID>"
|
|
{
|
|
TRACE_ALU_INPUT1 (GR[reg1]);
|
|
|
|
if (&PSW == &SR[regID])
|
|
PSW = (GR[reg1] & (CPU)->psw_mask);
|
|
else
|
|
SR[regID] = GR[reg1];
|
|
|
|
TRACE_ALU_RESULT (SR[regID]);
|
|
}
|
|
|
|
|
|
|
|
// MOV
|
|
rrrrr!0,000000,RRRRR:I:::mov
|
|
"mov r<reg1>, r<reg2>"
|
|
{
|
|
TRACE_ALU_INPUT0 ();
|
|
GR[reg2] = GR[reg1];
|
|
TRACE_ALU_RESULT (GR[reg2]);
|
|
}
|
|
|
|
|
|
rrrrr!0,010000,iiiii:II:::mov
|
|
"mov <imm5>, r<reg2>"
|
|
{
|
|
COMPAT_1 (OP_200 ());
|
|
}
|
|
|
|
00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
|
|
*v850e
|
|
*v850e1
|
|
"mov <imm32>, r<reg1>"
|
|
{
|
|
SAVE_2;
|
|
trace_input ("mov", OP_IMM_REG, 4);
|
|
State.regs[ OP[0] ] = load_mem (PC + 2, 4);
|
|
trace_output (OP_IMM_REG);
|
|
}
|
|
|
|
|
|
|
|
// MOVEA
|
|
rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
|
|
"movea <simm16>, r<reg1>, r<reg2>"
|
|
{
|
|
TRACE_ALU_INPUT2 (GR[reg1], simm16);
|
|
GR[reg2] = GR[reg1] + simm16;
|
|
TRACE_ALU_RESULT (GR[reg2]);
|
|
}
|
|
|
|
|
|
|
|
// MOVHI
|
|
rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
|
|
"movhi <uimm16>, r<reg1>, r<reg2>"
|
|
{
|
|
COMPAT_2 (OP_640 ());
|
|
}
|
|
|
|
|
|
|
|
// MUL
|
|
rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
|
|
*v850e
|
|
*v850e1
|
|
"mul r<reg1>, r<reg2>, r<reg3>"
|
|
{
|
|
COMPAT_2 (OP_22007E0 ());
|
|
}
|
|
|
|
rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
|
|
*v850e
|
|
*v850e1
|
|
"mul <imm9>, r<reg2>, r<reg3>"
|
|
{
|
|
COMPAT_2 (OP_24007E0 ());
|
|
}
|
|
|
|
|
|
// MULH
|
|
rrrrr!0,000111,RRRRR:I:::mulh
|
|
"mulh r<reg1>, r<reg2>"
|
|
{
|
|
COMPAT_1 (OP_E0 ());
|
|
}
|
|
|
|
rrrrr!0,010111,iiiii:II:::mulh
|
|
"mulh <imm5>, r<reg2>"
|
|
{
|
|
COMPAT_1 (OP_2E0 ());
|
|
}
|
|
|
|
|
|
|
|
// MULHI
|
|
rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
|
|
"mulhi <uimm16>, r<reg1>, r<reg2>"
|
|
{
|
|
COMPAT_2 (OP_6E0 ());
|
|
}
|
|
|
|
|
|
|
|
// MULU
|
|
rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
|
|
*v850e
|
|
*v850e1
|
|
"mulu r<reg1>, r<reg2>, r<reg3>"
|
|
{
|
|
COMPAT_2 (OP_22207E0 ());
|
|
}
|
|
|
|
rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
|
|
*v850e
|
|
*v850e1
|
|
"mulu <imm9>, r<reg2>, r<reg3>"
|
|
{
|
|
COMPAT_2 (OP_24207E0 ());
|
|
}
|
|
|
|
|
|
|
|
// NOP
|
|
0000000000000000:I:::nop
|
|
"nop"
|
|
{
|
|
/* do nothing, trace nothing */
|
|
}
|
|
|
|
|
|
|
|
// NOT
|
|
rrrrr,000001,RRRRR:I:::not
|
|
"not r<reg1>, r<reg2>"
|
|
{
|
|
COMPAT_1 (OP_20 ());
|
|
}
|
|
|
|
|
|
|
|
// NOT1
|
|
01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
|
|
"not1 <bit3>, <disp16>[r<reg1>]"
|
|
{
|
|
COMPAT_2 (OP_47C0 ());
|
|
}
|
|
|
|
rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
|
|
*v850e
|
|
*v850e1
|
|
"not1 r<reg2>, r<reg1>"
|
|
{
|
|
COMPAT_2 (OP_E207E0 ());
|
|
}
|
|
|
|
|
|
|
|
// OR
|
|
rrrrr,001000,RRRRR:I:::or
|
|
"or r<reg1>, r<reg2>"
|
|
{
|
|
COMPAT_1 (OP_100 ());
|
|
}
|
|
|
|
|
|
|
|
// ORI
|
|
rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
|
|
"ori <uimm16>, r<reg1>, r<reg2>"
|
|
{
|
|
COMPAT_2 (OP_680 ());
|
|
}
|
|
|
|
|
|
|
|
// PREPARE
|
|
0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
|
|
*v850e
|
|
*v850e1
|
|
"prepare <list12>, <imm5>"
|
|
{
|
|
int i;
|
|
SAVE_2;
|
|
|
|
trace_input ("prepare", OP_PUSHPOP1, 0);
|
|
|
|
/* Store the registers with lower number registers being placed at
|
|
higher addresses. */
|
|
for (i = 0; i < 12; i++)
|
|
if ((OP[3] & (1 << type1_regs[ i ])))
|
|
{
|
|
SP -= 4;
|
|
store_mem (SP, 4, State.regs[ 20 + i ]);
|
|
}
|
|
|
|
SP -= (OP[3] & 0x3e) << 1;
|
|
|
|
trace_output (OP_PUSHPOP1);
|
|
}
|
|
|
|
|
|
0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
|
|
*v850e
|
|
*v850e1
|
|
"prepare <list12>, <imm5>, sp"
|
|
{
|
|
COMPAT_2 (OP_30780 ());
|
|
}
|
|
|
|
0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
|
|
*v850e
|
|
*v850e1
|
|
"prepare <list12>, <imm5>, <uimm16>"
|
|
{
|
|
COMPAT_2 (OP_B0780 ());
|
|
}
|
|
|
|
0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
|
|
*v850e
|
|
*v850e1
|
|
"prepare <list12>, <imm5>, <uimm16>"
|
|
{
|
|
COMPAT_2 (OP_130780 ());
|
|
}
|
|
|
|
0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
|
|
*v850e
|
|
*v850e1
|
|
"prepare <list12>, <imm5>, <uimm32>"
|
|
{
|
|
COMPAT_2 (OP_1B0780 ());
|
|
}
|
|
|
|
|
|
|
|
// RETI
|
|
0000011111100000 + 0000000101000000:X:::reti
|
|
"reti"
|
|
{
|
|
if ((PSW & PSW_EP))
|
|
{
|
|
nia = (EIPC & ~1);
|
|
PSW = EIPSW;
|
|
}
|
|
else if ((PSW & PSW_NP))
|
|
{
|
|
nia = (FEPC & ~1);
|
|
PSW = FEPSW;
|
|
}
|
|
else
|
|
{
|
|
nia = (EIPC & ~1);
|
|
PSW = EIPSW;
|
|
}
|
|
TRACE_BRANCH1 (PSW);
|
|
}
|
|
|
|
|
|
|
|
// SAR
|
|
rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
|
|
"sar r<reg1>, r<reg2>"
|
|
{
|
|
COMPAT_2 (OP_A007E0 ());
|
|
}
|
|
|
|
rrrrr,010101,iiiii:II:::sar
|
|
"sar <imm5>, r<reg2>"
|
|
{
|
|
COMPAT_1 (OP_2A0 ());
|
|
}
|
|
|
|
|
|
|
|
// SASF
|
|
rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
|
|
*v850e
|
|
*v850e1
|
|
"sasf %s<cccc>, r<reg2>"
|
|
{
|
|
COMPAT_2 (OP_20007E0 ());
|
|
}
|
|
|
|
|
|
|
|
|
|
// SATADD
|
|
rrrrr!0,000110,RRRRR:I:::satadd
|
|
"satadd r<reg1>, r<reg2>"
|
|
{
|
|
COMPAT_1 (OP_C0 ());
|
|
}
|
|
|
|
rrrrr!0,010001,iiiii:II:::satadd
|
|
"satadd <imm5>, r<reg2>"
|
|
{
|
|
COMPAT_1 (OP_220 ());
|
|
}
|
|
|
|
|
|
|
|
// SATSUB
|
|
rrrrr!0,000101,RRRRR:I:::satsub
|
|
"satsub r<reg1>, r<reg2>"
|
|
{
|
|
COMPAT_1 (OP_A0 ());
|
|
}
|
|
|
|
|
|
|
|
// SATSUBI
|
|
rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
|
|
"satsubi <simm16>, r<reg1>, r<reg2>"
|
|
{
|
|
COMPAT_2 (OP_660 ());
|
|
}
|
|
|
|
|
|
|
|
// SATSUBR
|
|
rrrrr!0,000100,RRRRR:I:::satsubr
|
|
"satsubr r<reg1>, r<reg2>"
|
|
{
|
|
COMPAT_1 (OP_80 ());
|
|
}
|
|
|
|
|
|
|
|
// SETF
|
|
rrrrr,1111110,cccc + 0000000000000000:IX:::setf
|
|
"setf %s<cccc>, r<reg2>"
|
|
{
|
|
COMPAT_2 (OP_7E0 ());
|
|
}
|
|
|
|
|
|
|
|
// SET1
|
|
00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
|
|
"set1 <bit3>, <disp16>[r<reg1>]"
|
|
{
|
|
COMPAT_2 (OP_7C0 ());
|
|
}
|
|
|
|
rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
|
|
*v850e
|
|
*v850e1
|
|
"set1 r<reg2>, [r<reg1>]"
|
|
{
|
|
COMPAT_2 (OP_E007E0 ());
|
|
}
|
|
|
|
|
|
|
|
// SHL
|
|
rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
|
|
"shl r<reg1>, r<reg2>"
|
|
{
|
|
COMPAT_2 (OP_C007E0 ());
|
|
}
|
|
|
|
rrrrr,010110,iiiii:II:::shl
|
|
"shl <imm5>, r<reg2>"
|
|
{
|
|
COMPAT_1 (OP_2C0 ());
|
|
}
|
|
|
|
|
|
|
|
// SHR
|
|
rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
|
|
"shr r<reg1>, r<reg2>"
|
|
{
|
|
COMPAT_2 (OP_8007E0 ());
|
|
}
|
|
|
|
rrrrr,010100,iiiii:II:::shr
|
|
"shr <imm5>, r<reg2>"
|
|
{
|
|
COMPAT_1 (OP_280 ());
|
|
}
|
|
|
|
|
|
|
|
// SLD
|
|
rrrrr,0110,ddddddd:IV:::sld.b
|
|
"sld.bu <disp7>[ep], r<reg2>":(PSW & PSW_US)
|
|
"sld.b <disp7>[ep], r<reg2>"
|
|
{
|
|
unsigned32 addr = EP + disp7;
|
|
unsigned32 result = load_mem (addr, 1);
|
|
if (PSW & PSW_US)
|
|
{
|
|
GR[reg2] = result;
|
|
TRACE_LD_NAME ("sld.bu", addr, result);
|
|
}
|
|
else
|
|
{
|
|
result = EXTEND8 (result);
|
|
GR[reg2] = result;
|
|
TRACE_LD (addr, result);
|
|
}
|
|
}
|
|
|
|
rrrrr,1000,ddddddd:IV:::sld.h
|
|
"sld.hu <disp8>[ep], r<reg2>":(PSW & PSW_US)
|
|
"sld.h <disp8>[ep], r<reg2>"
|
|
{
|
|
unsigned32 addr = EP + disp8;
|
|
unsigned32 result = load_mem (addr, 2);
|
|
if (PSW & PSW_US)
|
|
{
|
|
GR[reg2] = result;
|
|
TRACE_LD_NAME ("sld.hu", addr, result);
|
|
}
|
|
else
|
|
{
|
|
result = EXTEND16 (result);
|
|
GR[reg2] = result;
|
|
TRACE_LD (addr, result);
|
|
}
|
|
}
|
|
|
|
rrrrr,1010,dddddd,0:IV:::sld.w
|
|
"sld.w <disp8>[ep], r<reg2>"
|
|
{
|
|
unsigned32 addr = EP + disp8;
|
|
unsigned32 result = load_mem (addr, 4);
|
|
GR[reg2] = result;
|
|
TRACE_LD (addr, result);
|
|
}
|
|
|
|
rrrrr!0,0000110,dddd:IV:::sld.bu
|
|
*v850e
|
|
*v850e1
|
|
"sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US)
|
|
"sld.bu <disp4>[ep], r<reg2>"
|
|
{
|
|
unsigned32 addr = EP + disp4;
|
|
unsigned32 result = load_mem (addr, 1);
|
|
if (PSW & PSW_US)
|
|
{
|
|
result = EXTEND8 (result);
|
|
GR[reg2] = result;
|
|
TRACE_LD_NAME ("sld.b", addr, result);
|
|
}
|
|
else
|
|
{
|
|
GR[reg2] = result;
|
|
TRACE_LD (addr, result);
|
|
}
|
|
}
|
|
|
|
rrrrr!0,0000111,dddd:IV:::sld.hu
|
|
*v850e
|
|
*v850e1
|
|
"sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US)
|
|
"sld.hu <disp5>[ep], r<reg2>"
|
|
{
|
|
unsigned32 addr = EP + disp5;
|
|
unsigned32 result = load_mem (addr, 2);
|
|
if (PSW & PSW_US)
|
|
{
|
|
result = EXTEND16 (result);
|
|
GR[reg2] = result;
|
|
TRACE_LD_NAME ("sld.h", addr, result);
|
|
}
|
|
else
|
|
{
|
|
GR[reg2] = result;
|
|
TRACE_LD (addr, result);
|
|
}
|
|
}
|
|
|
|
// SST
|
|
rrrrr,0111,ddddddd:IV:::sst.b
|
|
"sst.b r<reg2>, <disp7>[ep]"
|
|
{
|
|
COMPAT_1 (OP_380 ());
|
|
}
|
|
|
|
rrrrr,1001,ddddddd:IV:::sst.h
|
|
"sst.h r<reg2>, <disp8>[ep]"
|
|
{
|
|
COMPAT_1 (OP_480 ());
|
|
}
|
|
|
|
rrrrr,1010,dddddd,1:IV:::sst.w
|
|
"sst.w r<reg2>, <disp8>[ep]"
|
|
{
|
|
COMPAT_1 (OP_501 ());
|
|
}
|
|
|
|
// ST
|
|
rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
|
|
"st.b r<reg2>, <disp16>[r<reg1>]"
|
|
{
|
|
COMPAT_2 (OP_740 ());
|
|
}
|
|
|
|
rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
|
|
"st.h r<reg2>, <disp16>[r<reg1>]"
|
|
{
|
|
COMPAT_2 (OP_760 ());
|
|
}
|
|
|
|
rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
|
|
"st.w r<reg2>, <disp16>[r<reg1>]"
|
|
{
|
|
COMPAT_2 (OP_10760 ());
|
|
}
|
|
|
|
// STSR
|
|
rrrrr,111111,regID + 0000000001000000:IX:::stsr
|
|
"stsr s<regID>, r<reg2>"
|
|
{
|
|
TRACE_ALU_INPUT1 (SR[regID]);
|
|
GR[reg2] = SR[regID];
|
|
TRACE_ALU_RESULT (GR[reg2]);
|
|
}
|
|
|
|
// SUB
|
|
rrrrr,001101,RRRRR:I:::sub
|
|
"sub r<reg1>, r<reg2>"
|
|
{
|
|
COMPAT_1 (OP_1A0 ());
|
|
}
|
|
|
|
// SUBR
|
|
rrrrr,001100,RRRRR:I:::subr
|
|
"subr r<reg1>, r<reg2>"
|
|
{
|
|
COMPAT_1 (OP_180 ());
|
|
}
|
|
|
|
// SWITCH
|
|
00000000010,RRRRR:I:::switch
|
|
*v850e
|
|
*v850e1
|
|
"switch r<reg1>"
|
|
{
|
|
unsigned long adr;
|
|
SAVE_1;
|
|
trace_input ("switch", OP_REG, 0);
|
|
adr = (cia + 2) + (State.regs[ reg1 ] << 1);
|
|
nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1);
|
|
trace_output (OP_REG);
|
|
}
|
|
|
|
// SXB
|
|
00000000101,RRRRR:I:::sxb
|
|
*v850e
|
|
*v850e1
|
|
"sxb r<reg1>"
|
|
{
|
|
TRACE_ALU_INPUT1 (GR[reg1]);
|
|
GR[reg1] = EXTEND8 (GR[reg1]);
|
|
TRACE_ALU_RESULT (GR[reg1]);
|
|
}
|
|
|
|
// SXH
|
|
00000000111,RRRRR:I:::sxh
|
|
*v850e
|
|
*v850e1
|
|
"sxh r<reg1>"
|
|
{
|
|
TRACE_ALU_INPUT1 (GR[reg1]);
|
|
GR[reg1] = EXTEND16 (GR[reg1]);
|
|
TRACE_ALU_RESULT (GR[reg1]);
|
|
}
|
|
|
|
// TRAP
|
|
00000111111,iiiii + 0000000100000000:X:::trap
|
|
"trap <vector>"
|
|
{
|
|
COMPAT_2 (OP_10007E0 ());
|
|
}
|
|
|
|
// TST
|
|
rrrrr,001011,RRRRR:I:::tst
|
|
"tst r<reg1>, r<reg2>"
|
|
{
|
|
COMPAT_1 (OP_160 ());
|
|
}
|
|
|
|
// TST1
|
|
11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
|
|
"tst1 <bit3>, <disp16>[r<reg1>]"
|
|
{
|
|
COMPAT_2 (OP_C7C0 ());
|
|
}
|
|
|
|
rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
|
|
*v850e
|
|
*v850e1
|
|
"tst1 r<reg2>, [r<reg1>]"
|
|
{
|
|
COMPAT_2 (OP_E607E0 ());
|
|
}
|
|
|
|
// XOR
|
|
rrrrr,001001,RRRRR:I:::xor
|
|
"xor r<reg1>, r<reg2>"
|
|
{
|
|
COMPAT_1 (OP_120 ());
|
|
}
|
|
|
|
// XORI
|
|
rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
|
|
"xori <uimm16>, r<reg1>, r<reg2>"
|
|
{
|
|
COMPAT_2 (OP_6A0 ());
|
|
}
|
|
|
|
// ZXB
|
|
00000000100,RRRRR:I:::zxb
|
|
*v850e
|
|
*v850e1
|
|
"zxb r<reg1>"
|
|
{
|
|
TRACE_ALU_INPUT1 (GR[reg1]);
|
|
GR[reg1] = GR[reg1] & 0xff;
|
|
TRACE_ALU_RESULT (GR[reg1]);
|
|
}
|
|
|
|
// ZXH
|
|
00000000110,RRRRR:I:::zxh
|
|
*v850e
|
|
*v850e1
|
|
"zxh r<reg1>"
|
|
{
|
|
TRACE_ALU_INPUT1 (GR[reg1]);
|
|
GR[reg1] = GR[reg1] & 0xffff;
|
|
TRACE_ALU_RESULT (GR[reg1]);
|
|
}
|
|
|
|
// Right field must be zero so that it doesn't clash with DIVH
|
|
// Left field must be non-zero so that it doesn't clash with SWITCH
|
|
11111,000010,00000:I:::break
|
|
*v850
|
|
*v850e
|
|
{
|
|
sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
|
|
}
|
|
|
|
11111,000010,00000:I:::dbtrap
|
|
*v850e1
|
|
"dbtrap"
|
|
{
|
|
DBPC = cia + 2;
|
|
DBPSW = PSW;
|
|
PSW = PSW | (PSW_NP | PSW_EP | PSW_ID);
|
|
PC = 0x00000060;
|
|
nia = 0x00000060;
|
|
TRACE_BRANCH0 ();
|
|
}
|
|
|
|
// New breakpoint: 0x7E0 0x7E0
|
|
00000,111111,00000 + 00000,11111,100000:X:::ilgop
|
|
{
|
|
sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
|
|
}
|
|
|
|
// Return from debug trap: 0x146007e0
|
|
0000011111100000 + 0000000101000110:X:::dbret
|
|
*v850e1
|
|
"dbret"
|
|
{
|
|
nia = DBPC;
|
|
PSW = DBPSW;
|
|
TRACE_BRANCH1 (PSW);
|
|
}
|