binutils-gdb/gas/config/tc-i386-intel.c
H.J. Lu 43234a1e14 Add Intel AVX-512 support
binutils/

2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
	    Alexander Ivchenko  <alexander.ivchenko@intel.com>
	    Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
	    Sergey Lega  <sergey.s.lega@intel.com>
	    Anna Tikhonova  <anna.tikhonova@intel.com>
	    Ilya Tocar  <ilya.tocar@intel.com>
	    Andrey Turetskiy  <andrey.turetskiy@intel.com>
	    Ilya Verbin  <ilya.verbin@intel.com>
	    Kirill Yukhin  <kirill.yukhin@intel.com>
	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>

	* dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and
	numeration in comments.
	(dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to
	dwarf table.

gas/

2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
	    Alexander Ivchenko  <alexander.ivchenko@intel.com>
	    Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
	    Sergey Lega  <sergey.s.lega@intel.com>
	    Anna Tikhonova  <anna.tikhonova@intel.com>
	    Ilya Tocar  <ilya.tocar@intel.com>
	    Andrey Turetskiy  <andrey.turetskiy@intel.com>
	    Ilya Verbin  <ilya.verbin@intel.com>
	    Kirill Yukhin  <kirill.yukhin@intel.com>
	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>

	* config/tc-i386-intel.c (O_zmmword_ptr): New.
	(i386_types): Add zmmword.
	(i386_intel_simplify_register): Allow regzmm.
	(i386_intel_simplify): Handle zmmwords.
	(i386_intel_operand): Handle RC/SAE, vector operations and
	zmmwords.
	* config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New.
	(struct RC_Operation): New.
	(struct Mask_Operation): New.
	(struct Broadcast_Operation): New.
	(vex_prefix): Size of bytes increased to 4 to support EVEX
	encoding.
	(enum i386_error): Add new error codes: unsupported_broadcast,
	broadcast_not_on_src_operand, broadcast_needed,
	unsupported_masking, mask_not_on_destination, no_default_mask,
	unsupported_rc_sae, rc_sae_operand_not_last_imm,
	invalid_register_operand, try_vector_disp8.
	(struct _i386_insn): Add new fields vrex, need_vrex, mask,
	rounding, broadcast, memshift.
	(struct RC_name): New.
	(RC_NamesTable): New.
	(evexlig): New.
	(evexwig): New.
	(extra_symbol_chars): Add '{'.
	(cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF.
	(i386_operand_type): Add regzmm, regmask and vec_disp8.
	(match_mem_size): Handle zmmwords.
	(operand_type_match): Handle zmm-registers.
	(mode_from_disp_size): Handle vec_disp8.
	(fits_in_vec_disp8): New.
	(md_begin): Handle {} properly.
	(type_names): Add "rZMM", "Mask reg" and "Vector d8".
	(build_vex_prefix): Handle vrex.
	(build_evex_prefix): New.
	(process_immext): Adjust to properly handle EVEX.
	(md_assemble): Add EVEX encoding support.
	(swap_2_operands): Correctly handle operands with masking,
	broadcasting or RC/SAE.
	(check_VecOperands): Support EVEX features.
	(VEX_check_operands): Properly handle 16 upper [xyz]mm registers.
	(match_template): Support regzmm and handle new error codes.
	(process_suffix): Handle zmmwords and zmm-registers.
	(check_byte_reg): Extend to zmm-registers.
	(process_operands): Extend to zmm-registers.
	(build_modrm_byte): Handle EVEX.
	(output_insn): Adjust to properly handle EVEX case.
	(disp_size): Handle vec_disp8.
	(output_disp): Support compressed disp8*N evex feature.
	(output_imm): Handle RC/SAE immediates properly.
	(check_VecOperations): New.
	(i386_immediate): Handle EVEX features.
	(i386_index_check): Handle zmmwords and zmm-registers.
	(RC_SAE_immediate): New.
	(i386_att_operand): Handle EVEX features.
	(parse_real_register): Add a check for ZMM/Mask registers.
	(OPTION_MEVEXLIG): New.
	(OPTION_MEVEXWIG): New.
	(md_longopts): Add mevexlig and mevexwig.
	(md_parse_option): Handle mevexlig and mevexwig options.
	(md_show_usage): Add description for mevexlig and mevexwig.
	* doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd,
	avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig.

gas/testsuite/

2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
	    Alexander Ivchenko  <alexander.ivchenko@intel.com>
	    Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
	    Sergey Lega  <sergey.s.lega@intel.com>
	    Anna Tikhonova  <anna.tikhonova@intel.com>
	    Ilya Tocar  <ilya.tocar@intel.com>
	    Andrey Turetskiy  <andrey.turetskiy@intel.com>
	    Ilya Verbin  <ilya.verbin@intel.com>
	    Kirill Yukhin  <kirill.yukhin@intel.com>
	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>

	* gas/cfi/cfi-i386.s: Add tests for k0-k7.
	* gas/cfi/cfi-i386.d: Change to reflect above mentioned changes.
	* gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7.
	* gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes.
	* gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto.
	* gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers.
	* gas/i386/intel-regs.d: Change correspondingly.
	* gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1.
	* gas/i386/prefetch.d: Ditto.
	* gas/i386/x86-64-prefetch-intel.d: Ditto.
	* gas/i386/x86-64-prefetch.d: Ditto.
	* gas/i386/avx512f-intel.d: New.
	* gas/i386/avx512f-nondef.d: New.
	* gas/i386/avx512f-nondef.s: New.
	* gas/i386/avx512f-opts-intel.d: New.
	* gas/i386/avx512f-opts.d: New.
	* gas/i386/avx512f-opts.s: New.
	* gas/i386/avx512f.d: New.
	* gas/i386/avx512f.s: New.
	* gas/i386/avx512cd-intel.d: New.
	* gas/i386/avx512cd.d: New.
	* gas/i386/avx512cd.s: New.
	* gas/i386/avx512er-intel.d: New.
	* gas/i386/avx512er.d: New.
	* gas/i386/avx512er.s: New.
	* gas/i386/avx512pf-intel.d: New.
	* gas/i386/avx512pf.d: New.
	* gas/i386/avx512pf.s: New.
	* gas/i386/evex-lig.s: New.
	* gas/i386/evex-lig256-intel.d: New.
	* gas/i386/evex-lig256.d: New.
	* gas/i386/evex-lig512-intel.d: New.
	* gas/i386/evex-lig512.d: New.
	* gas/i386/evex-wig.s: New.
	* gas/i386/evex-wig1-intel.d: New.
	* gas/i386/evex-wig1.d: New.
	* gas/i386/inval-avx512f.l: New.
	* gas/i386/inval-avx512f.s: New.
	* gas/i386/x86-64-avx512f-intel.d: New.
	* gas/i386/x86-64-avx512f-nondef.d: New.
	* gas/i386/x86-64-avx512f-nondef.s: New.
	* gas/i386/x86-64-avx512f-opts-intel.d: New.
	* gas/i386/x86-64-avx512f-opts.d: New.
	* gas/i386/x86-64-avx512f-opts.s: New.
	* gas/i386/x86-64-avx512f.d: New.
	* gas/i386/x86-64-avx512f.s: New.
	* gas/i386/x86-64-avx512cd-intel.d: New.
	* gas/i386/x86-64-avx512cd.d: New.
	* gas/i386/x86-64-avx512cd.s: New.
	* gas/i386/x86-64-avx512er-intel.d: New.
	* gas/i386/x86-64-avx512er.d: New.
	* gas/i386/x86-64-avx512er.s: New.
	* gas/i386/x86-64-avx512pf-intel.d: New.
	* gas/i386/x86-64-avx512pf.d: New.
	* gas/i386/x86-64-avx512pf.s: New.
	* gas/i386/x86-64-evex-lig.s: New.
	* gas/i386/x86-64-evex-lig256-intel.d: New.
	* gas/i386/x86-64-evex-lig256.d: New.
	* gas/i386/x86-64-evex-lig512-intel.d: New.
	* gas/i386/x86-64-evex-lig512.d: New.
	* gas/i386/x86-64-evex-wig.s: New.
	* gas/i386/x86-64-evex-wig1-intel.d: New.
	* gas/i386/x86-64-evex-wig1.d: New.
	* gas/i386/x86-64-inval-avx512f.l: New.
	* gas/i386/x86-64-inval-avx512f.s: New.
	* gas/i386/i386.exp: Run new AVX-512 tests.

opcodes/

2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
	    Alexander Ivchenko  <alexander.ivchenko@intel.com>
	    Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
	    Sergey Lega  <sergey.s.lega@intel.com>
	    Anna Tikhonova  <anna.tikhonova@intel.com>
	    Ilya Tocar  <ilya.tocar@intel.com>
	    Andrey Turetskiy  <andrey.turetskiy@intel.com>
	    Ilya Verbin  <ilya.verbin@intel.com>
	    Kirill Yukhin  <kirill.yukhin@intel.com>
	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>

	* i386-dis-evex.h: New.
	* i386-dis.c (OP_Rounding): New.
	(VPCMP_Fixup): New.
	(OP_Mask): New.
	(Rdq): New.
	(XMxmmq): New.
	(EXdScalarS): New.
	(EXymm): New.
	(EXEvexHalfBcstXmmq): New.
	(EXxmm_mdq): New.
	(EXEvexXGscat): New.
	(EXEvexXNoBcst): New.
	(VPCMP): New.
	(EXxEVexR): New.
	(EXxEVexS): New.
	(XMask): New.
	(MaskG): New.
	(MaskE): New.
	(MaskR): New.
	(MaskVex): New.
	(modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
	evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
	evex_rounding_mode, evex_sae_mode, mask_mode.
	(USE_EVEX_TABLE): New.
	(EVEX_TABLE): New.
	(EVEX enum): New.
	(REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
	REG_EVEX_0F38C7.
	(MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
	MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
	MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
	MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
	MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,  MOD_EVEX_0F38C7_REG_5,
	MOD_EVEX_0F38C7_REG_6.
	(PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
	PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
	PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
	PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
	PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
	PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
	PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
	PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
	PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
	PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
	PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
	PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
	PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
	PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
	PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
	PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
	PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
	PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
	PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
	PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
	PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
	PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
	PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
	PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
	PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
	PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
	PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
	PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
	PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
	PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
	PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
	PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
	PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
	PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
	PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
	PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
	PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
	PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
	PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
	PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
	PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
	PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
	PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
	PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
	PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
	PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
	PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
	PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
	PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
	PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
	PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
	PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
	PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
	PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
	PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
	PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
	PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
	PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
	PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
	PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
	PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
	PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
	PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
	PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
	PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
	PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
	PREFIX_EVEX_0F3A00,  PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
	PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
	PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
	PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
	PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
	PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
	PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
	PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
	PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
	PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
	PREFIX_EVEX_0F3A55.
	(VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
	VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
	VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
	VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
	VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
	VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
	VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
	VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
	VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
	VEX_W_0F3A32_P_2_LEN_0.
	(VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
	EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
	EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
	EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
	EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
	EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
	EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
	EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
	EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
	EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
	EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
	EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
	EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
	EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
	EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
	EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
	EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
	EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
	EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
	EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
	EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
	EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
	EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
	EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
	EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
	EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
	EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
	EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
	EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
	EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
	EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
	EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
	EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
	EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
	EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
	EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
	EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
	EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
	EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
	EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
	EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
	EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
	EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
	EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
	EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
	EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
	EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
	EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
	EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
	EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
	EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
	EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
	EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
	EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
	(struct vex): Add fields evex, r, v, mask_register_specifier,
	zeroing, ll, b.
	(intel_names_xmm): Add upper 16 registers.
	(att_names_xmm): Ditto.
	(intel_names_ymm): Ditto.
	(att_names_ymm): Ditto.
	(names_zmm): New.
	(intel_names_zmm): Ditto.
	(att_names_zmm): Ditto.
	(names_mask): Ditto.
	(intel_names_mask): Ditto.
	(att_names_mask): Ditto.
	(names_rounding): Ditto.
	(names_broadcast): Ditto.
	(x86_64_table): Add escape to evex-table.
	(reg_table): Include reg_table evex-entries from
	i386-dis-evex.h.  Fix prefetchwt1 instruction.
	(prefix_table): Add entries for new instructions.
	(vex_table): Ditto.
	(vex_len_table): Ditto.
	(vex_w_table): Ditto.
	(mod_table): Ditto.
	(get_valid_dis386): Properly handle new instructions.
	(print_insn): Handle zmm and mask registers, print mask operand.
	(intel_operand_size): Support EVEX, new modes and sizes.
	(OP_E_register): Handle new modes.
	(OP_E_memory): Ditto.
	(OP_G): Ditto.
	(OP_XMM): Ditto.
	(OP_EX): Ditto.
	(OP_VEX): Ditto.
	* i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
	CPU_ANY_AVX_FLAGS.  Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
	CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
	(cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
	CpuAVX512PF and CpuVREX.
	(operand_type_init): Add OPERAND_TYPE_REGZMM,
	OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
	(opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
	StaticRounding, SAE, Disp8MemShift, NoDefMask.
	(operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
	* i386-init.h: Regenerate.
	* i386-opc.h (CpuAVX512F): New.
	(CpuAVX512CD): New.
	(CpuAVX512ER): New.
	(CpuAVX512PF): New.
	(CpuVREX): New.
	(i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
	cpuavx512pf and cpuvrex fields.
	(VecSIB): Add VecSIB512.
	(EVex): New.
	(Masking): New.
	(VecESize): New.
	(Broadcast): New.
	(StaticRounding): New.
	(SAE): New.
	(Disp8MemShift): New.
	(NoDefMask): New.
	(i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
	staticrounding, sae, disp8memshift and nodefmask.
	(RegZMM): New.
	(Zmmword): Ditto.
	(Vec_Disp8): Ditto.
	(i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
	fields.
	(RegVRex): New.
	* i386-opc.tbl: Add AVX512 instructions.
	* i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
	registers, mask registers.
	* i386-tbl.h: Regenerate.
2013-07-26 17:20:25 +00:00

1004 lines
26 KiB
C

/* tc-i386.c -- Assemble Intel syntax code for ix86/x86-64
Copyright 2009, 2010
Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
static struct
{
operatorT op_modifier; /* Operand modifier. */
int is_mem; /* 1 if operand is memory reference. */
int is_indirect; /* 1 if operand is indirect reference. */
int has_offset; /* 1 if operand has offset. */
unsigned int in_offset; /* >=1 if processing operand of offset. */
unsigned int in_bracket; /* >=1 if processing operand in brackets. */
unsigned int in_scale; /* >=1 if processing multipication operand
* in brackets. */
i386_operand_type reloc_types; /* Value obtained from lex_got(). */
const reg_entry *base; /* Base register (if any). */
const reg_entry *index; /* Index register (if any). */
offsetT scale_factor; /* Accumulated scale factor. */
symbolS *seg;
}
intel_state;
/* offset X_add_symbol */
#define O_offset O_md32
/* offset X_add_symbol */
#define O_short O_md31
/* near ptr X_add_symbol */
#define O_near_ptr O_md30
/* far ptr X_add_symbol */
#define O_far_ptr O_md29
/* byte ptr X_add_symbol */
#define O_byte_ptr O_md28
/* word ptr X_add_symbol */
#define O_word_ptr O_md27
/* dword ptr X_add_symbol */
#define O_dword_ptr O_md26
/* qword ptr X_add_symbol */
#define O_qword_ptr O_md25
/* oword ptr X_add_symbol */
#define O_oword_ptr O_md24
/* fword ptr X_add_symbol */
#define O_fword_ptr O_md23
/* tbyte ptr X_add_symbol */
#define O_tbyte_ptr O_md22
/* xmmword ptr X_add_symbol */
#define O_xmmword_ptr O_md21
/* ymmword ptr X_add_symbol */
#define O_ymmword_ptr O_md20
/* zmmword ptr X_add_symbol */
#define O_zmmword_ptr O_md19
static struct
{
const char *name;
operatorT op;
unsigned int operands;
}
const i386_operators[] =
{
{ "and", O_bit_and, 2 },
{ "eq", O_eq, 2 },
{ "ge", O_ge, 2 },
{ "gt", O_gt, 2 },
{ "le", O_le, 2 },
{ "lt", O_lt, 2 },
{ "mod", O_modulus, 2 },
{ "ne", O_ne, 2 },
{ "not", O_bit_not, 1 },
{ "offset", O_offset, 1 },
{ "or", O_bit_inclusive_or, 2 },
{ "shl", O_left_shift, 2 },
{ "short", O_short, 1 },
{ "shr", O_right_shift, 2 },
{ "xor", O_bit_exclusive_or, 2 },
{ NULL, O_illegal, 0 }
};
static struct
{
const char *name;
operatorT op;
unsigned short sz[3];
}
const i386_types[] =
{
#define I386_TYPE(t, n) { #t, O_##t##_ptr, { n, n, n } }
I386_TYPE(byte, 1),
I386_TYPE(word, 2),
I386_TYPE(dword, 4),
I386_TYPE(fword, 6),
I386_TYPE(qword, 8),
I386_TYPE(tbyte, 10),
I386_TYPE(oword, 16),
I386_TYPE(xmmword, 16),
I386_TYPE(ymmword, 32),
I386_TYPE(zmmword, 64),
#undef I386_TYPE
{ "near", O_near_ptr, { 0xff04, 0xff02, 0xff08 } },
{ "far", O_far_ptr, { 0xff06, 0xff05, 0xff06 } },
{ NULL, O_illegal, { 0, 0, 0 } }
};
operatorT i386_operator (const char *name, unsigned int operands, char *pc)
{
unsigned int j;
if (!intel_syntax)
return O_absent;
if (!name)
{
if (operands != 2)
return O_illegal;
switch (*input_line_pointer)
{
case ':':
++input_line_pointer;
return O_full_ptr;
case '[':
++input_line_pointer;
return O_index;
case '@':
if (this_operand >= 0 && i.reloc[this_operand] == NO_RELOC)
{
int adjust = 0;
char *gotfree_input_line = lex_got (&i.reloc[this_operand],
&adjust,
&intel_state.reloc_types);
if (!gotfree_input_line)
break;
free (gotfree_input_line);
*input_line_pointer++ = '+';
memset (input_line_pointer, '0', adjust - 1);
input_line_pointer[adjust - 1] = ' ';
return O_add;
}
break;
}
return O_illegal;
}
for (j = 0; i386_operators[j].name; ++j)
if (strcasecmp (i386_operators[j].name, name) == 0)
{
if (i386_operators[j].operands
&& i386_operators[j].operands != operands)
return O_illegal;
return i386_operators[j].op;
}
for (j = 0; i386_types[j].name; ++j)
if (strcasecmp (i386_types[j].name, name) == 0)
break;
if (i386_types[j].name && *pc == ' ')
{
char *pname = ++input_line_pointer;
char c = get_symbol_end ();
if (strcasecmp (pname, "ptr") == 0)
{
pname[-1] = *pc;
*pc = c;
if (intel_syntax > 0 || operands != 1)
return O_illegal;
return i386_types[j].op;
}
*input_line_pointer = c;
input_line_pointer = pname - 1;
}
return O_absent;
}
static int i386_intel_parse_name (const char *name, expressionS *e)
{
unsigned int j;
if (! strcmp (name, "$"))
{
current_location (e);
return 1;
}
for (j = 0; i386_types[j].name; ++j)
if (strcasecmp(i386_types[j].name, name) == 0)
{
e->X_op = O_constant;
e->X_add_number = i386_types[j].sz[flag_code];
e->X_add_symbol = NULL;
e->X_op_symbol = NULL;
return 1;
}
return 0;
}
static INLINE int i386_intel_check (const reg_entry *rreg,
const reg_entry *base,
const reg_entry *iindex)
{
if ((this_operand >= 0
&& rreg != i.op[this_operand].regs)
|| base != intel_state.base
|| iindex != intel_state.index)
{
as_bad (_("invalid use of register"));
return 0;
}
return 1;
}
static INLINE void i386_intel_fold (expressionS *e, symbolS *sym)
{
expressionS *exp = symbol_get_value_expression (sym);
if (S_GET_SEGMENT (sym) == absolute_section)
{
offsetT val = e->X_add_number;
*e = *exp;
e->X_add_number += val;
}
else
{
if (exp->X_op == O_symbol
&& strcmp (S_GET_NAME (exp->X_add_symbol),
GLOBAL_OFFSET_TABLE_NAME) == 0)
sym = exp->X_add_symbol;
e->X_add_symbol = sym;
e->X_op_symbol = NULL;
e->X_op = O_symbol;
}
}
static int
i386_intel_simplify_register (expressionS *e)
{
int reg_num;
if (this_operand < 0 || intel_state.in_offset)
{
as_bad (_("invalid use of register"));
return 0;
}
if (e->X_op == O_register)
reg_num = e->X_add_number;
else
reg_num = e->X_md - 1;
if (!intel_state.in_bracket)
{
if (i.op[this_operand].regs)
{
as_bad (_("invalid use of register"));
return 0;
}
if (i386_regtab[reg_num].reg_type.bitfield.sreg3
&& i386_regtab[reg_num].reg_num == RegFlat)
{
as_bad (_("invalid use of pseudo-register"));
return 0;
}
i.op[this_operand].regs = i386_regtab + reg_num;
}
else if (!intel_state.index
&& (i386_regtab[reg_num].reg_type.bitfield.regxmm
|| i386_regtab[reg_num].reg_type.bitfield.regymm
|| i386_regtab[reg_num].reg_type.bitfield.regzmm))
intel_state.index = i386_regtab + reg_num;
else if (!intel_state.base && !intel_state.in_scale)
intel_state.base = i386_regtab + reg_num;
else if (!intel_state.index)
{
if (intel_state.in_scale
|| i386_regtab[reg_num].reg_type.bitfield.baseindex)
intel_state.index = i386_regtab + reg_num;
else
{
/* Convert base to index and make ESP/RSP the base. */
intel_state.index = intel_state.base;
intel_state.base = i386_regtab + reg_num;
}
}
else
{
/* esp is invalid as index */
intel_state.index = i386_regtab + REGNAM_EAX + ESP_REG_NUM;
}
return 2;
}
static int i386_intel_simplify (expressionS *);
static INLINE int i386_intel_simplify_symbol(symbolS *sym)
{
int ret = i386_intel_simplify (symbol_get_value_expression (sym));
if (ret == 2)
{
S_SET_SEGMENT(sym, absolute_section);
ret = 1;
}
return ret;
}
static int i386_intel_simplify (expressionS *e)
{
const reg_entry *the_reg = (this_operand >= 0
? i.op[this_operand].regs : NULL);
const reg_entry *base = intel_state.base;
const reg_entry *state_index = intel_state.index;
int ret;
if (!intel_syntax)
return 1;
switch (e->X_op)
{
case O_index:
if (e->X_add_symbol)
{
if (!i386_intel_simplify_symbol (e->X_add_symbol)
|| !i386_intel_check(the_reg, intel_state.base,
intel_state.index))
return 0;
}
if (!intel_state.in_offset)
++intel_state.in_bracket;
ret = i386_intel_simplify_symbol (e->X_op_symbol);
if (!intel_state.in_offset)
--intel_state.in_bracket;
if (!ret)
return 0;
if (e->X_add_symbol)
e->X_op = O_add;
else
i386_intel_fold (e, e->X_op_symbol);
break;
case O_offset:
intel_state.has_offset = 1;
++intel_state.in_offset;
ret = i386_intel_simplify_symbol (e->X_add_symbol);
--intel_state.in_offset;
if (!ret || !i386_intel_check(the_reg, base, state_index))
return 0;
i386_intel_fold (e, e->X_add_symbol);
return ret;
case O_byte_ptr:
case O_word_ptr:
case O_dword_ptr:
case O_fword_ptr:
case O_qword_ptr:
case O_tbyte_ptr:
case O_oword_ptr:
case O_xmmword_ptr:
case O_ymmword_ptr:
case O_zmmword_ptr:
case O_near_ptr:
case O_far_ptr:
if (intel_state.op_modifier == O_absent)
intel_state.op_modifier = e->X_op;
/* FALLTHROUGH */
case O_short:
if (symbol_get_value_expression (e->X_add_symbol)->X_op
== O_register)
{
as_bad (_("invalid use of register"));
return 0;
}
if (!i386_intel_simplify_symbol (e->X_add_symbol))
return 0;
i386_intel_fold (e, e->X_add_symbol);
break;
case O_full_ptr:
if (symbol_get_value_expression (e->X_op_symbol)->X_op
== O_register)
{
as_bad (_("invalid use of register"));
return 0;
}
if (!i386_intel_simplify_symbol (e->X_op_symbol)
|| !i386_intel_check(the_reg, intel_state.base,
intel_state.index))
return 0;
if (!intel_state.in_offset)
intel_state.seg = e->X_add_symbol;
i386_intel_fold (e, e->X_op_symbol);
break;
case O_multiply:
if (this_operand >= 0 && intel_state.in_bracket)
{
expressionS *scale = NULL;
if (intel_state.index)
--scale;
if (!intel_state.in_scale++)
intel_state.scale_factor = 1;
ret = i386_intel_simplify_symbol (e->X_add_symbol);
if (ret && !scale && intel_state.index)
scale = symbol_get_value_expression (e->X_op_symbol);
if (ret)
ret = i386_intel_simplify_symbol (e->X_op_symbol);
if (ret && !scale && intel_state.index)
scale = symbol_get_value_expression (e->X_add_symbol);
if (ret && scale && (scale + 1))
{
resolve_expression (scale);
if (scale->X_op != O_constant
|| intel_state.index->reg_type.bitfield.reg16)
scale->X_add_number = 0;
intel_state.scale_factor *= scale->X_add_number;
}
--intel_state.in_scale;
if (!ret)
return 0;
if (!intel_state.in_scale)
switch (intel_state.scale_factor)
{
case 1:
i.log2_scale_factor = 0;
break;
case 2:
i.log2_scale_factor = 1;
break;
case 4:
i.log2_scale_factor = 2;
break;
case 8:
i.log2_scale_factor = 3;
break;
default:
/* esp is invalid as index */
intel_state.index = i386_regtab + REGNAM_EAX + ESP_REG_NUM;
break;
}
break;
}
goto fallthrough;
case O_register:
ret = i386_intel_simplify_register (e);
if (ret == 2)
{
gas_assert (e->X_add_number < (unsigned short) -1);
e->X_md = (unsigned short) e->X_add_number + 1;
e->X_op = O_constant;
e->X_add_number = 0;
}
return ret;
case O_constant:
if (e->X_md)
return i386_intel_simplify_register (e);
/* FALLTHROUGH */
default:
fallthrough:
if (e->X_add_symbol
&& !i386_intel_simplify_symbol (e->X_add_symbol))
return 0;
if (e->X_op == O_add || e->X_op == O_subtract)
{
base = intel_state.base;
state_index = intel_state.index;
}
if (!i386_intel_check (the_reg, base, state_index)
|| (e->X_op_symbol
&& !i386_intel_simplify_symbol (e->X_op_symbol))
|| !i386_intel_check (the_reg,
(e->X_op != O_add
? base : intel_state.base),
(e->X_op != O_add
? state_index : intel_state.index)))
return 0;
break;
}
if (this_operand >= 0
&& e->X_op == O_symbol
&& !intel_state.in_offset)
{
segT seg = S_GET_SEGMENT (e->X_add_symbol);
if (seg != absolute_section
&& seg != reg_section
&& seg != expr_section)
intel_state.is_mem |= 2 - !intel_state.in_bracket;
}
return 1;
}
int i386_need_index_operator (void)
{
return intel_syntax < 0;
}
static int
i386_intel_operand (char *operand_string, int got_a_float)
{
char *saved_input_line_pointer, *buf;
segT exp_seg;
expressionS exp, *expP;
char suffix = 0;
int ret;
/* Handle vector immediates. */
if (RC_SAE_immediate (operand_string))
return 1;
/* Initialize state structure. */
intel_state.op_modifier = O_absent;
intel_state.is_mem = 0;
intel_state.is_indirect = 0;
intel_state.has_offset = 0;
intel_state.base = NULL;
intel_state.index = NULL;
intel_state.seg = NULL;
operand_type_set (&intel_state.reloc_types, ~0);
gas_assert (!intel_state.in_offset);
gas_assert (!intel_state.in_bracket);
gas_assert (!intel_state.in_scale);
saved_input_line_pointer = input_line_pointer;
input_line_pointer = buf = xstrdup (operand_string);
intel_syntax = -1;
memset (&exp, 0, sizeof(exp));
exp_seg = expression (&exp);
ret = i386_intel_simplify (&exp);
intel_syntax = 1;
SKIP_WHITESPACE ();
/* Handle vector operations. */
if (*input_line_pointer == '{')
{
char *end = check_VecOperations (input_line_pointer, NULL);
if (end)
input_line_pointer = end;
else
ret = 0;
}
if (!is_end_of_line[(unsigned char) *input_line_pointer])
{
as_bad (_("junk `%s' after expression"), input_line_pointer);
ret = 0;
}
else if (exp.X_op == O_illegal || exp.X_op == O_absent)
{
as_bad (_("invalid expression"));
ret = 0;
}
else if (!intel_state.has_offset
&& input_line_pointer > buf
&& *(input_line_pointer - 1) == ']')
{
intel_state.is_mem |= 1;
intel_state.is_indirect = 1;
}
input_line_pointer = saved_input_line_pointer;
free (buf);
gas_assert (!intel_state.in_offset);
gas_assert (!intel_state.in_bracket);
gas_assert (!intel_state.in_scale);
if (!ret)
return 0;
if (intel_state.op_modifier != O_absent
&& current_templates->start->base_opcode != 0x8d /* lea */)
{
i.types[this_operand].bitfield.unspecified = 0;
switch (intel_state.op_modifier)
{
case O_byte_ptr:
i.types[this_operand].bitfield.byte = 1;
suffix = BYTE_MNEM_SUFFIX;
break;
case O_word_ptr:
i.types[this_operand].bitfield.word = 1;
if ((current_templates->start->name[0] == 'l'
&& current_templates->start->name[2] == 's'
&& current_templates->start->name[3] == 0)
|| current_templates->start->base_opcode == 0x62 /* bound */)
suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
else if (got_a_float == 2) /* "fi..." */
suffix = SHORT_MNEM_SUFFIX;
else
suffix = WORD_MNEM_SUFFIX;
break;
case O_dword_ptr:
i.types[this_operand].bitfield.dword = 1;
if ((current_templates->start->name[0] == 'l'
&& current_templates->start->name[2] == 's'
&& current_templates->start->name[3] == 0)
|| current_templates->start->base_opcode == 0x62 /* bound */)
suffix = WORD_MNEM_SUFFIX;
else if (flag_code == CODE_16BIT
&& (current_templates->start->opcode_modifier.jump
|| current_templates->start->opcode_modifier.jumpdword))
suffix = LONG_DOUBLE_MNEM_SUFFIX;
else if (got_a_float == 1) /* "f..." */
suffix = SHORT_MNEM_SUFFIX;
else
suffix = LONG_MNEM_SUFFIX;
break;
case O_fword_ptr:
i.types[this_operand].bitfield.fword = 1;
if (current_templates->start->name[0] == 'l'
&& current_templates->start->name[2] == 's'
&& current_templates->start->name[3] == 0)
suffix = LONG_MNEM_SUFFIX;
else if (!got_a_float)
{
if (flag_code == CODE_16BIT)
add_prefix (DATA_PREFIX_OPCODE);
suffix = LONG_DOUBLE_MNEM_SUFFIX;
}
else
suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
break;
case O_qword_ptr:
i.types[this_operand].bitfield.qword = 1;
if (current_templates->start->base_opcode == 0x62 /* bound */
|| got_a_float == 1) /* "f..." */
suffix = LONG_MNEM_SUFFIX;
else
suffix = QWORD_MNEM_SUFFIX;
break;
case O_tbyte_ptr:
i.types[this_operand].bitfield.tbyte = 1;
if (got_a_float == 1)
suffix = LONG_DOUBLE_MNEM_SUFFIX;
else
suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
break;
case O_oword_ptr:
case O_xmmword_ptr:
i.types[this_operand].bitfield.xmmword = 1;
suffix = XMMWORD_MNEM_SUFFIX;
break;
case O_ymmword_ptr:
i.types[this_operand].bitfield.ymmword = 1;
suffix = YMMWORD_MNEM_SUFFIX;
break;
case O_zmmword_ptr:
i.types[this_operand].bitfield.zmmword = 1;
suffix = ZMMWORD_MNEM_SUFFIX;
break;
case O_far_ptr:
suffix = LONG_DOUBLE_MNEM_SUFFIX;
/* FALLTHROUGH */
case O_near_ptr:
if (!current_templates->start->opcode_modifier.jump
&& !current_templates->start->opcode_modifier.jumpdword)
suffix = got_a_float /* so it will cause an error */
? BYTE_MNEM_SUFFIX
: LONG_DOUBLE_MNEM_SUFFIX;
break;
default:
BAD_CASE (intel_state.op_modifier);
break;
}
if (!i.suffix)
i.suffix = suffix;
else if (i.suffix != suffix)
{
as_bad (_("conflicting operand size modifiers"));
return 0;
}
}
/* Operands for jump/call need special consideration. */
if (current_templates->start->opcode_modifier.jump
|| current_templates->start->opcode_modifier.jumpdword
|| current_templates->start->opcode_modifier.jumpintersegment)
{
if (i.op[this_operand].regs
|| intel_state.base
|| intel_state.index
|| intel_state.is_mem > 1)
i.types[this_operand].bitfield.jumpabsolute = 1;
else
switch (intel_state.op_modifier)
{
case O_near_ptr:
if (intel_state.seg)
i.types[this_operand].bitfield.jumpabsolute = 1;
else
intel_state.is_mem = 1;
break;
case O_far_ptr:
case O_absent:
if (!intel_state.seg)
{
intel_state.is_mem = 1;
if (intel_state.op_modifier == O_absent)
{
if (intel_state.is_indirect == 1)
i.types[this_operand].bitfield.jumpabsolute = 1;
break;
}
as_bad (_("cannot infer the segment part of the operand"));
return 0;
}
else if (S_GET_SEGMENT (intel_state.seg) == reg_section)
i.types[this_operand].bitfield.jumpabsolute = 1;
else
{
i386_operand_type types;
if (i.imm_operands >= MAX_IMMEDIATE_OPERANDS)
{
as_bad (_("at most %d immediate operands are allowed"),
MAX_IMMEDIATE_OPERANDS);
return 0;
}
expP = &im_expressions[i.imm_operands++];
memset (expP, 0, sizeof(*expP));
expP->X_op = O_symbol;
expP->X_add_symbol = intel_state.seg;
i.op[this_operand].imms = expP;
resolve_expression (expP);
operand_type_set (&types, ~0);
if (!i386_finalize_immediate (S_GET_SEGMENT (intel_state.seg),
expP, types, operand_string))
return 0;
if (i.operands < MAX_OPERANDS)
{
this_operand = i.operands++;
i.types[this_operand].bitfield.unspecified = 1;
}
if (suffix == LONG_DOUBLE_MNEM_SUFFIX)
i.suffix = 0;
intel_state.seg = NULL;
intel_state.is_mem = 0;
}
break;
default:
i.types[this_operand].bitfield.jumpabsolute = 1;
break;
}
if (i.types[this_operand].bitfield.jumpabsolute)
intel_state.is_mem |= 1;
}
else if (intel_state.seg)
intel_state.is_mem |= 1;
if (i.op[this_operand].regs)
{
i386_operand_type temp;
/* Register operand. */
if (intel_state.base || intel_state.index || intel_state.seg)
{
as_bad (_("invalid operand"));
return 0;
}
temp = i.op[this_operand].regs->reg_type;
temp.bitfield.baseindex = 0;
i.types[this_operand] = operand_type_or (i.types[this_operand],
temp);
i.types[this_operand].bitfield.unspecified = 0;
++i.reg_operands;
}
else if (intel_state.base
|| intel_state.index
|| intel_state.seg
|| intel_state.is_mem)
{
/* Memory operand. */
if ((int) i.mem_operands
>= 2 - !current_templates->start->opcode_modifier.isstring)
{
/* Handle
call 0x9090,0x90909090
lcall 0x9090,0x90909090
jmp 0x9090,0x90909090
ljmp 0x9090,0x90909090
*/
if ((current_templates->start->opcode_modifier.jumpintersegment
|| current_templates->start->opcode_modifier.jumpdword
|| current_templates->start->opcode_modifier.jump)
&& this_operand == 1
&& intel_state.seg == NULL
&& i.mem_operands == 1
&& i.disp_operands == 1
&& intel_state.op_modifier == O_absent)
{
/* Try to process the first operand as immediate, */
this_operand = 0;
if (i386_finalize_immediate (exp_seg, i.op[0].imms,
intel_state.reloc_types,
NULL))
{
this_operand = 1;
expP = &im_expressions[0];
i.op[this_operand].imms = expP;
*expP = exp;
/* Try to process the second operand as immediate, */
if (i386_finalize_immediate (exp_seg, expP,
intel_state.reloc_types,
NULL))
{
i.mem_operands = 0;
i.disp_operands = 0;
i.imm_operands = 2;
i.types[0].bitfield.mem = 0;
i.types[0].bitfield.disp16 = 0;
i.types[0].bitfield.disp32 = 0;
i.types[0].bitfield.disp32s = 0;
return 1;
}
}
}
as_bad (_("too many memory references for `%s'"),
current_templates->start->name);
return 0;
}
expP = &disp_expressions[i.disp_operands];
memcpy (expP, &exp, sizeof(exp));
resolve_expression (expP);
if (expP->X_op != O_constant
|| expP->X_add_number
|| (!intel_state.base
&& !intel_state.index))
{
i.op[this_operand].disps = expP;
i.disp_operands++;
if (flag_code == CODE_64BIT)
{
i.types[this_operand].bitfield.disp32 = 1;
if (!i.prefix[ADDR_PREFIX])
{
i.types[this_operand].bitfield.disp64 = 1;
i.types[this_operand].bitfield.disp32s = 1;
}
}
else if (!i.prefix[ADDR_PREFIX] ^ (flag_code == CODE_16BIT))
i.types[this_operand].bitfield.disp32 = 1;
else
i.types[this_operand].bitfield.disp16 = 1;
#if defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)
/*
* exp_seg is used only for verification in
* i386_finalize_displacement, and we can end up seeing reg_section
* here - but we know we removed all registers from the expression
* (or error-ed on any remaining ones) in i386_intel_simplify. I
* consider the check in i386_finalize_displacement bogus anyway, in
* particular because it doesn't allow for expr_section, so I'd
* rather see that check (and the similar one in
* i386_finalize_immediate) use SEG_NORMAL(), but not being an a.out
* expert I can't really say whether that would have other bad side
* effects.
*/
if (OUTPUT_FLAVOR == bfd_target_aout_flavour
&& exp_seg == reg_section)
exp_seg = expP->X_op != O_constant ? undefined_section
: absolute_section;
#endif
if (!i386_finalize_displacement (exp_seg, expP,
intel_state.reloc_types,
operand_string))
return 0;
}
if (intel_state.base || intel_state.index)
i.types[this_operand].bitfield.baseindex = 1;
if (intel_state.seg)
{
for (;;)
{
expP = symbol_get_value_expression (intel_state.seg);
if (expP->X_op != O_full_ptr)
break;
intel_state.seg = expP->X_add_symbol;
}
if (expP->X_op != O_register)
{
as_bad (_("segment register name expected"));
return 0;
}
if (!i386_regtab[expP->X_add_number].reg_type.bitfield.sreg2
&& !i386_regtab[expP->X_add_number].reg_type.bitfield.sreg3)
{
as_bad (_("invalid use of register"));
return 0;
}
switch (i386_regtab[expP->X_add_number].reg_num)
{
case 0: i.seg[i.mem_operands] = &es; break;
case 1: i.seg[i.mem_operands] = &cs; break;
case 2: i.seg[i.mem_operands] = &ss; break;
case 3: i.seg[i.mem_operands] = &ds; break;
case 4: i.seg[i.mem_operands] = &fs; break;
case 5: i.seg[i.mem_operands] = &gs; break;
case RegFlat: i.seg[i.mem_operands] = NULL; break;
}
}
/* Swap base and index in 16-bit memory operands like
[si+bx]. Since i386_index_check is also used in AT&T
mode we have to do that here. */
if (intel_state.base
&& intel_state.index
&& intel_state.base->reg_type.bitfield.reg16
&& intel_state.index->reg_type.bitfield.reg16
&& intel_state.base->reg_num >= 6
&& intel_state.index->reg_num < 6)
{
i.base_reg = intel_state.index;
i.index_reg = intel_state.base;
}
else
{
i.base_reg = intel_state.base;
i.index_reg = intel_state.index;
}
if (!i386_index_check (operand_string))
return 0;
i.types[this_operand].bitfield.mem = 1;
++i.mem_operands;
}
else
{
/* Immediate. */
if (i.imm_operands >= MAX_IMMEDIATE_OPERANDS)
{
as_bad (_("at most %d immediate operands are allowed"),
MAX_IMMEDIATE_OPERANDS);
return 0;
}
expP = &im_expressions[i.imm_operands++];
i.op[this_operand].imms = expP;
*expP = exp;
return i386_finalize_immediate (exp_seg, expP, intel_state.reloc_types,
operand_string);
}
return 1;
}