Jim Blandy c0efbca4a3 * mips.igen (CFC1, CTC1): Pass the correct register numbers to ... PENDING_FILL. Use PENDING_SCHED directly to handle the pending set of the FCSR. * sim-main.h (COCIDX): Remove definition; this isn't supported by PENDING_FILL, and you can get the intended effect gracefully by calling PENDING_SCHED directly.		2001-04-12 14:53:20 +00:00
..
acconfig.h
ChangeLog	* mips.igen (CFC1, CTC1): Pass the correct register numbers to	2001-04-12 14:53:20 +00:00
config.in
configure	Change profiling so that it is enabled by default. Re-generate everything.	2000-05-24 04:39:50 +00:00
configure.in	import gdb-19990422 snapshot	1999-04-26 18:34:20 +00:00
dv-tx3904cpu.c
dv-tx3904irc.c
dv-tx3904sio.c	import gdb-1999-12-06 snapshot	1999-12-07 03:56:43 +00:00
dv-tx3904tmr.c
interp.c	2001-02-19 Ben Elliston <bje@redhat.com>	2001-02-19 21:57:03 +00:00
m16.dc
m16.igen	* m16.igen (break): Call SignalException not sim_engine_halt.	2000-07-20 00:02:22 +00:00
m16run.c
Makefile.in	Don't clean *.igen.	2000-07-27 12:03:19 +00:00
mips.dc
mips.igen	* mips.igen (CFC1, CTC1): Pass the correct register numbers to	2001-04-12 14:53:20 +00:00
sim-main.c	2001-02-08 Ben Elliston <bje@redhat.com>	2001-02-08 05:22:04 +00:00
sim-main.h	* mips.igen (CFC1, CTC1): Pass the correct register numbers to	2001-04-12 14:53:20 +00:00
tconfig.in	import gdb-1999-07-12 snapshot	1999-07-12 11:15:22 +00:00
tx.igen	import gdb-1999-09-08 snapshot	1999-09-09 00:02:17 +00:00
vr.igen