Nick Clifton d99ff40fae * v850.igen (W,WWWW): Correct computation of register number. ... (JR32): Remove unnecessary comma. (cmovf.s): Register 0 is an invalid source register. (maddf.s): Remove bogus intermediary rounding. (nmaddf.s): Likewise. (trncf.sl): Remove bogus initial rounding. (trncf.dw): Likewise. (trncf.sl): Likewise. (trncf.sw): Likewise.		2012-09-13 08:09:26 +00:00
..
arm	PR sim/14540	2012-09-03 10:13:11 +00:00
avr
bfin	sim: bfin: set bfrom alias field to correct size	2012-08-01 03:31:55 +00:00
common	sim: cr16: update syscall list	2012-08-30 07:05:19 +00:00
cr16	sim: cr16: improve trap handling	2012-08-30 06:10:28 +00:00
cris
d10v	include "config.h" instead of BFD's sysdep.h in d10v/interp.c	2012-06-19 22:46:57 +00:00
erc32	oops - acxidentally omitted from previous delta.	2012-08-16 08:38:45 +00:00
frv
h8300
igen
iq2000
lm32
m32c
m32r
m68hc11
mcore
microblaze
mips	2012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>	2012-09-04 21:40:46 +00:00
mn10300
moxie	Adjust for branch target encoding change	2012-09-08 01:26:07 +00:00
ppc
rl78
rx
sh
sh64
testsuite
v850	* v850.igen (W,WWWW): Correct computation of register number.	2012-09-13 08:09:26 +00:00
.gitignore
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configure
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configure.tgt
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