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Allow zero operand in sparc VIS3 cmask patterns.

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* config/sparc/sparc.md (cmask patterns): Allow zero operand.

From-SVN: r180715
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David S. Miller 2011-10-31 22:09:12 +00:00 committed by David S. Miller
parent 7e547d7b31
commit 015e8b63f4
2 changed files with 5 additions and 3 deletions
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2
gcc/ChangeLog
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@ -1,5 +1,7 @@
2011-10-31 David S. Miller <davem@davemloft.net>
* config/sparc/sparc.md (cmask patterns): Allow zero operand.
* dwarf2out.c (cached_next_real_insn): New.
(dwarf2out_end_epilogue): Set it to NULL_RTX.
(dwarf2out_var_location): Remove cached_next_real_insn local static.

6
gcc/config/sparc/sparc.md
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@ -8452,7 +8452,7 @@
;; Conditional moves are possible via fcmpX --> cmaskX -> bshuffle
(define_insn "cmask8<P:mode>_vis"
[(set (reg:DI GSR_REG)
(unspec:DI [(match_operand:P 0 "register_operand" "r")
(unspec:DI [(match_operand:P 0 "register_or_zero_operand" "rJ")
(reg:DI GSR_REG)]
UNSPEC_CMASK8))]
"TARGET_VIS3"
@ -8460,7 +8460,7 @@
(define_insn "cmask16<P:mode>_vis"
[(set (reg:DI GSR_REG)
(unspec:DI [(match_operand:P 0 "register_operand" "r")
(unspec:DI [(match_operand:P 0 "register_or_zero_operand" "rJ")
(reg:DI GSR_REG)]
UNSPEC_CMASK16))]
"TARGET_VIS3"
@ -8468,7 +8468,7 @@
(define_insn "cmask32<P:mode>_vis"
[(set (reg:DI GSR_REG)
(unspec:DI [(match_operand:P 0 "register_operand" "r")
(unspec:DI [(match_operand:P 0 "register_or_zero_operand" "rJ")
(reg:DI GSR_REG)]
UNSPEC_CMASK32))]
"TARGET_VIS3"