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AArch64 backend support for SBC instruction. 

From-SVN: r196797
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Ian Bolton 2013-03-19 16:23:08 +00:00 committed by Ian Bolton
parent 5977a10d4a
commit 0b8cdc5869
3 changed files with 37 additions and 0 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2013-03-19 Ian Bolton <ian.bolton@arm.com>
* config/aarch64/aarch64.md (*sub<mode>3_carryin): New pattern.
(*subsi3_carryin_uxtw): Likewise.
2013-03-19 Ian Bolton <ian.bolton@arm.com>
* config/aarch64/aarch64.md (*ror<mode>3_insn): New pattern.

28
gcc/config/aarch64/aarch64.md
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@ -1790,6 +1790,34 @@
(set_attr "mode" "SI")]
)
(define_insn "*sub<mode>3_carryin"
[(set
(match_operand:GPI 0 "register_operand" "=r")
(minus:GPI (minus:GPI
(match_operand:GPI 1 "register_operand" "r")
(ltu:GPI (reg:CC CC_REGNUM) (const_int 0)))
(match_operand:GPI 2 "register_operand" "r")))]
""
"sbc\\t%<w>0, %<w>1, %<w>2"
[(set_attr "v8type" "adc")
(set_attr "mode" "<MODE>")]
)
;; zero_extend version of the above
(define_insn "*subsi3_carryin_uxtw"
[(set
(match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(minus:SI (minus:SI
(match_operand:SI 1 "register_operand" "r")
(ltu:SI (reg:CC CC_REGNUM) (const_int 0)))
(match_operand:SI 2 "register_operand" "r"))))]
""
"sbc\\t%w0, %w1, %w2"
[(set_attr "v8type" "adc")
(set_attr "mode" "SI")]
)
(define_insn "*sub_uxt<mode>_multp2"
[(set (match_operand:GPI 0 "register_operand" "=rk")
(minus:GPI (match_operand:GPI 4 "register_operand" "r")

4
gcc/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2013-03-19 Ian Bolton <ian.bolton@arm.com>
* gcc.target/aarch64/sbc.c: New test.
2013-03-19 Ian Bolton <ian.bolton@arm.com>
* gcc.target/aarch64/ror.c: New test.