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AArch64 backend support for ROR instruction. 

From-SVN: r196796
This commit is contained in:
Ian Bolton 2013-03-19 16:18:46 +00:00 committed by Ian Bolton
parent bd83ff2c67
commit 5977a10d4a
3 changed files with 37 additions and 0 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2013-03-19 Ian Bolton <ian.bolton@arm.com>
* config/aarch64/aarch64.md (*ror<mode>3_insn): New pattern.
(*rorsi3_insn_uxtw): Likewise.
2013-03-19 Ian Bolton <ian.bolton@arm.com>
* config/aarch64/aarch64.md (*extr<mode>5_insn): New pattern.

28
gcc/config/aarch64/aarch64.md
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@ -2731,6 +2731,34 @@
(set_attr "mode" "SI")]
)
(define_insn "*ror<mode>3_insn"
[(set (match_operand:GPI 0 "register_operand" "=r")
(rotate:GPI (match_operand:GPI 1 "register_operand" "r")
(match_operand 2 "const_int_operand" "n")))]
"UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
{
operands[3] = GEN_INT (<sizen> - UINTVAL (operands[2]));
return "ror\\t%<w>0, %<w>1, %3";
}
[(set_attr "v8type" "shift")
(set_attr "mode" "<MODE>")]
)
;; zero_extend version of the above
(define_insn "*rorsi3_insn_uxtw"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(rotate:SI (match_operand:SI 1 "register_operand" "r")
(match_operand 2 "const_int_operand" "n"))))]
"UINTVAL (operands[2]) < 32"
{
operands[3] = GEN_INT (32 - UINTVAL (operands[2]));
return "ror\\t%w0, %w1, %3";
}
[(set_attr "v8type" "shift")
(set_attr "mode" "SI")]
)
(define_insn "*<ANY_EXTEND:optab><GPI:mode>_ashl<SHORT:mode>"
[(set (match_operand:GPI 0 "register_operand" "=r")
(ANY_EXTEND:GPI

4
gcc/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2013-03-19 Ian Bolton <ian.bolton@arm.com>
* gcc.target/aarch64/ror.c: New test.
2013-03-19 Ian Bolton <ian.bolton@arm.com>
* gcc.target/aarch64/extr.c: New test.