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AArch64 backend support for EXTR instruction. 

From-SVN: r196795
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Ian Bolton 2013-03-19 16:17:14 +00:00 committed by Ian Bolton
parent ba65123cbe
commit bd83ff2c67
3 changed files with 37 additions and 0 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2013-03-19 Ian Bolton <ian.bolton@arm.com>
* config/aarch64/aarch64.md (*extr<mode>5_insn): New pattern.
(*extrsi5_insn_uxtw): Likewise.
2013-03-19 Richard Biener <rguenther@suse.de>
PR tree-optimization/56273

28
gcc/config/aarch64/aarch64.md
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@ -2703,6 +2703,34 @@
(set_attr "mode" "<MODE>")]
)
(define_insn "*extr<mode>5_insn"
[(set (match_operand:GPI 0 "register_operand" "=r")
(ior:GPI (ashift:GPI (match_operand:GPI 1 "register_operand" "r")
(match_operand 3 "const_int_operand" "n"))
(lshiftrt:GPI (match_operand:GPI 2 "register_operand" "r")
(match_operand 4 "const_int_operand" "n"))))]
"UINTVAL (operands[3]) < GET_MODE_BITSIZE (<MODE>mode) &&
(UINTVAL (operands[3]) + UINTVAL (operands[4]) == GET_MODE_BITSIZE (<MODE>mode))"
"extr\\t%<w>0, %<w>1, %<w>2, %4"
[(set_attr "v8type" "shift")
(set_attr "mode" "<MODE>")]
)
;; zero_extend version of the above
(define_insn "*extrsi5_insn_uxtw"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
(match_operand 3 "const_int_operand" "n"))
(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
(match_operand 4 "const_int_operand" "n")))))]
"UINTVAL (operands[3]) < 32 &&
(UINTVAL (operands[3]) + UINTVAL (operands[4]) == 32)"
"extr\\t%w0, %w1, %w2, %4"
[(set_attr "v8type" "shift")
(set_attr "mode" "SI")]
)
(define_insn "*<ANY_EXTEND:optab><GPI:mode>_ashl<SHORT:mode>"
[(set (match_operand:GPI 0 "register_operand" "=r")
(ANY_EXTEND:GPI

4
gcc/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2013-03-19 Ian Bolton <ian.bolton@arm.com>
* gcc.target/aarch64/extr.c: New test.
2013-03-19 Richard Biener <rguenther@suse.de>
PR tree-optimization/56273