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* doc/invoke.texi: Document AMD bdver1 and btver1.

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Venkataramanan Kumar 2011-11-16 17:31:38 +00:00 committed by Harsha Jagasia
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@ -1,3 +1,7 @@
2011-11-16 Venkataramanan Kumar <venkataramanan.kumar@amd.com>
* doc/invoke.texi: Document AMD bdver1 and btver1.
2011-11-16 Richard Earnshaw <rearnsha@arm.com>
Bernd Schmidt <bernds@coudesourcery.com>
Sebastian Huber <sebastian.huber@embedded-brains.de>

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gcc/doc/invoke.texi
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@ -12803,6 +12803,15 @@ Improved versions of k8, opteron and athlon64 with SSE3 instruction set support.
AMD Family 10h core based CPUs with x86-64 instruction set support. (This
supersets MMX, SSE, SSE2, SSE3, SSE4A, 3DNow!, enhanced 3DNow!, ABM and 64-bit
instruction set extensions.)
@item bdver1
AMD Family 15h core based CPUs with x86-64 instruction set support. (This
supersets FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A,
SSSE3, SSE4.1, SSE4.2, 3DNow!, enhanced 3DNow!, ABM and 64-bit
instruction set extensions.)
@item btver1
AMD Family 14h core based CPUs with x86-64 instruction set support. (This
supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit
instruction set extensions.)
@item winchip-c6
IDT Winchip C6 CPU, dealt in same way as i486 with additional MMX instruction
set support.