[ARM] PR68532 Fix up vzip recognition for big endian
gcc/ChangeLog:
2016-02-09 Charles Baylis <charles.baylis@linaro.org>
PR target/68532
* config/arm/arm.c (arm_evpc_neon_vzip): Allow for big endian lane
order.
* config/arm/arm_neon.h (vzipq_s8): Adjust shuffle patterns for big
endian.
(vzipq_s16): Likewise.
(vzipq_s32): Likewise.
(vzipq_f32): Likewise.
(vzipq_u8): Likewise.
(vzipq_u16): Likewise.
(vzipq_u32): Likewise.
(vzipq_p8): Likewise.
(vzipq_p16): Likewise.
From-SVN: r233252
This commit is contained in:
Charles Baylis
Charles Baylis
parent
4b79ac23c6
commit
1149b83cbd
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@ -1,3 +1,19 @@
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2016-02-09 Charles Baylis <charles.baylis@linaro.org>
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PR target/68532
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* config/arm/arm.c (arm_evpc_neon_vzip): Allow for big endian lane
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order.
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* config/arm/arm_neon.h (vzipq_s8): Adjust shuffle patterns for big
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endian.
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(vzipq_s16): Likewise.
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(vzipq_s32): Likewise.
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(vzipq_f32): Likewise.
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(vzipq_u8): Likewise.
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(vzipq_u16): Likewise.
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(vzipq_u32): Likewise.
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(vzipq_p8): Likewise.
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(vzipq_p16): Likewise.
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2016-02-09 Charles Baylis <charles.baylis@linaro.org>
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PR target/68532
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@ -28313,15 +28313,20 @@ arm_evpc_neon_vzip (struct expand_vec_perm_d *d)
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unsigned int i, high, mask, nelt = d->nelt;
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rtx out0, out1, in0, in1;
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rtx (*gen)(rtx, rtx, rtx, rtx);
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int first_elem;
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bool is_swapped;
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if (GET_MODE_UNIT_SIZE (d->vmode) >= 8)
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return false;
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/* Note that these are little-endian tests. Adjust for big-endian later. */
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is_swapped = BYTES_BIG_ENDIAN;
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first_elem = d->perm[neon_endian_lane_map (d->vmode, 0) ^ is_swapped];
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high = nelt / 2;
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if (d->perm[0] == high)
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if (first_elem == neon_endian_lane_map (d->vmode, high))
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;
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else if (d->perm[0] == 0)
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else if (first_elem == neon_endian_lane_map (d->vmode, 0))
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high = 0;
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else
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return false;
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@ -28329,11 +28334,15 @@ arm_evpc_neon_vzip (struct expand_vec_perm_d *d)
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for (i = 0; i < nelt / 2; i++)
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{
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unsigned elt = (i + high) & mask;
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if (d->perm[i * 2] != elt)
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unsigned elt =
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neon_pair_endian_lane_map (d->vmode, i + high) & mask;
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if (d->perm[neon_pair_endian_lane_map (d->vmode, 2 * i + is_swapped)]
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!= elt)
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return false;
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elt = (elt + nelt) & mask;
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if (d->perm[i * 2 + 1] != elt)
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elt =
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neon_pair_endian_lane_map (d->vmode, i + nelt + high) & mask;
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if (d->perm[neon_pair_endian_lane_map (d->vmode, 2 * i + !is_swapped)]
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!= elt)
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return false;
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}
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@ -28357,11 +28366,8 @@ arm_evpc_neon_vzip (struct expand_vec_perm_d *d)
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in0 = d->op0;
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in1 = d->op1;
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if (BYTES_BIG_ENDIAN)
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{
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std::swap (in0, in1);
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high = !high;
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}
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if (is_swapped)
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std::swap (in0, in1);
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out0 = d->target;
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out1 = gen_reg_rtx (d->vmode);
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@ -8453,9 +8453,9 @@ vzipq_s8 (int8x16_t __a, int8x16_t __b)
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int8x16x2_t __rv;
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#ifdef __ARM_BIG_ENDIAN
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint8x16_t)
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{ 24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15 });
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{ 20, 4, 21, 5, 22, 6, 23, 7, 16, 0, 17, 1, 18, 2, 19, 3 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint8x16_t)
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{ 16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7 });
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{ 28, 12, 29, 13, 30, 14, 31, 15, 24, 8, 25, 9, 26, 10, 27, 11 });
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#else
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint8x16_t)
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{ 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 });
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@ -8471,9 +8471,9 @@ vzipq_s16 (int16x8_t __a, int16x8_t __b)
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int16x8x2_t __rv;
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#ifdef __ARM_BIG_ENDIAN
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint16x8_t)
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{ 12, 4, 13, 5, 14, 6, 15, 7 });
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{ 10, 2, 11, 3, 8, 0, 9, 1 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint16x8_t)
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{ 8, 0, 9, 1, 10, 2, 11, 3 });
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{ 14, 6, 15, 7, 12, 4, 13, 5 });
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#else
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint16x8_t)
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{ 0, 8, 1, 9, 2, 10, 3, 11 });
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@ -8488,8 +8488,8 @@ vzipq_s32 (int32x4_t __a, int32x4_t __b)
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{
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int32x4x2_t __rv;
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#ifdef __ARM_BIG_ENDIAN
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint32x4_t) { 6, 2, 7, 3 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint32x4_t) { 4, 0, 5, 1 });
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint32x4_t) { 5, 1, 4, 0 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint32x4_t) { 7, 3, 6, 2 });
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#else
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint32x4_t) { 0, 4, 1, 5 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint32x4_t) { 2, 6, 3, 7 });
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@ -8502,8 +8502,8 @@ vzipq_f32 (float32x4_t __a, float32x4_t __b)
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{
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float32x4x2_t __rv;
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#ifdef __ARM_BIG_ENDIAN
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint32x4_t) { 6, 2, 7, 3 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint32x4_t) { 4, 0, 5, 1 });
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint32x4_t) { 5, 1, 4, 0 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint32x4_t) { 7, 3, 6, 2 });
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#else
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint32x4_t) { 0, 4, 1, 5 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint32x4_t) { 2, 6, 3, 7 });
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@ -8517,9 +8517,9 @@ vzipq_u8 (uint8x16_t __a, uint8x16_t __b)
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uint8x16x2_t __rv;
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#ifdef __ARM_BIG_ENDIAN
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint8x16_t)
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{ 24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15 });
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{ 20, 4, 21, 5, 22, 6, 23, 7, 16, 0, 17, 1, 18, 2, 19, 3 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint8x16_t)
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{ 16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7 });
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{ 28, 12, 29, 13, 30, 14, 31, 15, 24, 8, 25, 9, 26, 10, 27, 11 });
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#else
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint8x16_t)
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{ 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 });
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@ -8535,9 +8535,9 @@ vzipq_u16 (uint16x8_t __a, uint16x8_t __b)
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uint16x8x2_t __rv;
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#ifdef __ARM_BIG_ENDIAN
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint16x8_t)
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{ 12, 4, 13, 5, 14, 6, 15, 7 });
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{ 10, 2, 11, 3, 8, 0, 9, 1 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint16x8_t)
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{ 8, 0, 9, 1, 10, 2, 11, 3 });
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{ 14, 6, 15, 7, 12, 4, 13, 5 });
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#else
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint16x8_t)
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{ 0, 8, 1, 9, 2, 10, 3, 11 });
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@ -8552,8 +8552,8 @@ vzipq_u32 (uint32x4_t __a, uint32x4_t __b)
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{
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uint32x4x2_t __rv;
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#ifdef __ARM_BIG_ENDIAN
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint32x4_t) { 6, 2, 7, 3 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint32x4_t) { 4, 0, 5, 1 });
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint32x4_t) { 5, 1, 4, 0 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint32x4_t) { 7, 3, 6, 2 });
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#else
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint32x4_t) { 0, 4, 1, 5 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint32x4_t) { 2, 6, 3, 7 });
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@ -8567,9 +8567,9 @@ vzipq_p8 (poly8x16_t __a, poly8x16_t __b)
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poly8x16x2_t __rv;
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#ifdef __ARM_BIG_ENDIAN
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint8x16_t)
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{ 24, 8, 25, 9, 26, 10, 27, 11, 28, 12, 29, 13, 30, 14, 31, 15 });
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{ 20, 4, 21, 5, 22, 6, 23, 7, 16, 0, 17, 1, 18, 2, 19, 3 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint8x16_t)
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{ 16, 0, 17, 1, 18, 2, 19, 3, 20, 4, 21, 5, 22, 6, 23, 7 });
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{ 28, 12, 29, 13, 30, 14, 31, 15, 24, 8, 25, 9, 26, 10, 27, 11 });
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#else
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint8x16_t)
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{ 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 });
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@ -8585,9 +8585,9 @@ vzipq_p16 (poly16x8_t __a, poly16x8_t __b)
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poly16x8x2_t __rv;
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#ifdef __ARM_BIG_ENDIAN
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint16x8_t)
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{ 12, 4, 13, 5, 14, 6, 15, 7 });
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{ 10, 2, 11, 3, 8, 0, 9, 1 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint16x8_t)
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{ 8, 0, 9, 1, 10, 2, 11, 3 });
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{ 14, 6, 15, 7, 12, 4, 13, 5 });
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#else
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint16x8_t)
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{ 0, 8, 1, 9, 2, 10, 3, 11 });
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