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mips-cpus.def (octeon+): New CPU.

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2011-12-08  Andrew Pinski  <apinski@cavium.com>

	* config/mips/mips-cpus.def (octeon+): New CPU.
	* config/mips/mips-tables.opt: Regenerate.
	* config/mips/mips.h (MIPS_CPP_SET_PROCESSOR): Emit '+' as 'P'.



2011-12-08  Andrew Pinski  <apinski@cavium.com>

	* cc.target/mips/mult-1.c: Forbid all Octeon processors.
	* gcc.target/mips/dmult-1.c: Likewise.
	* gcc.target/mips/branch-1.c: Likewise.
	* gcc.target/mips/extend-1.c: Likewise.

From-SVN: r182152
This commit is contained in:
Andrew Pinski 2011-12-09 03:56:36 +00:00 committed by Andrew Pinski
parent fbf7be801c
commit 14f2a7e2b1
9 changed files with 25 additions and 5 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2011-12-08 Andrew Pinski <apinski@cavium.com>
* config/mips/mips-cpus.def (octeon+): New CPU.
* config/mips/mips-tables.opt: Regenerate.
* config/mips/mips.h (MIPS_CPP_SET_PROCESSOR): Emit '+' as 'P'.
2011-12-08 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR middle-end/39976

1
gcc/config/mips/mips-cpus.def
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@ -145,3 +145,4 @@ MIPS_CPU ("loongson3a", PROCESSOR_LOONGSON_3A, 64, PTF_AVOID_BRANCHLIKELY)
/* MIPS64 Release 2 processors. */
MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY)

3
gcc/config/mips/mips-tables.opt
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@ -603,3 +603,6 @@ Enum(mips_arch_opt_value) String(loongson3a) Value(79) Canonical
EnumValue
Enum(mips_arch_opt_value) String(octeon) Value(80) Canonical
EnumValue
Enum(mips_arch_opt_value) String(octeon+) Value(81) Canonical

5
gcc/config/mips/mips.h
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@ -329,7 +329,10 @@ struct mips_cpu_info {
\
macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
for (p = macro; *p != 0; p++) \
*p = TOUPPER (*p); \
if (*p == '+') \
*p = 'P'; \
else \
*p = TOUPPER (*p); \
\
builtin_define (macro); \
builtin_define_with_value ((PREFIX), (INFO)->name, 1); \

7
gcc/testsuite/ChangeLog
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@ -1,3 +1,10 @@
2011-12-08 Andrew Pinski <apinski@cavium.com>
* cc.target/mips/mult-1.c: Forbid all Octeon processors.
* gcc.target/mips/dmult-1.c: Likewise.
* gcc.target/mips/branch-1.c: Likewise.
* gcc.target/mips/extend-1.c: Likewise.
2011-12-08 Jason Merrill <jason@redhat.com>
PR c++/51318

2
gcc/testsuite/gcc.target/mips/branch-1.c
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@ -2,7 +2,7 @@
but we test for "bbit" elsewhere. On other targets, we should implement
the "if" statements using an "andi" instruction followed by a branch
on zero. */
/* { dg-options "-O2 forbid_cpu=octeon" } */
/* { dg-options "-O2 forbid_cpu=octeon.*" } */
void bar (void);
NOMIPS16 void f1 (int x) { if (x & 4) bar (); }

2
gcc/testsuite/gcc.target/mips/dmult-1.c
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@ -1,4 +1,4 @@
/* { dg-options "forbid_cpu=octeon -mgp64" } */
/* { dg-options "forbid_cpu=octeon.* -mgp64" } */
/* { dg-final { scan-assembler "\tdmult\t" } } */
/* { dg-final { scan-assembler "\tmflo\t" } } */
/* { dg-final { scan-assembler-not "\tdmul\t" } } */

2
gcc/testsuite/gcc.target/mips/extend-1.c
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@ -1,4 +1,4 @@
/* { dg-options "-O -mgp64 forbid_cpu=octeon" } */
/* { dg-options "-O -mgp64 forbid_cpu=octeon.*" } */
/* { dg-final { scan-assembler-times "\tdsll\t" 5 } } */
/* { dg-final { scan-assembler-times "\tdsra\t" 5 } } */
/* { dg-final { scan-assembler-not "\tsll\t" } } */

2
gcc/testsuite/gcc.target/mips/mult-1.c
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@ -1,6 +1,6 @@
/* For SI->DI widening multiplication we should use DINS to combine the two
halves. For Octeon use DMUL with explicit widening. */
/* { dg-options "-O -mgp64 isa_rev>=2 forbid_cpu=octeon" } */
/* { dg-options "-O -mgp64 isa_rev>=2 forbid_cpu=octeon.*" } */
/* { dg-final { scan-assembler "\tdins\t" } } */
/* { dg-final { scan-assembler-not "\tdsll\t" } } */
/* { dg-final { scan-assembler-not "\tdsrl\t" } } */