re PR target/63965 (ICE: in extract_constrain_insn, at recog.c:2230 on ppc64)
2014-11-24 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/63965 * config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Do not set Altivec & -16 mask if the type is not valid for Altivec registers. (rs6000_secondary_reload_memory): Add support for ((reg + const) + reg) that occurs during push_reload processing. * config/rs6000/altivec.md (altivec_mov<mode>): Add instruction alternative for moving constant vectors which are easy altivec constants to GPRs. Set the length attribute each of the alternatives. From-SVN: r218028
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@ -1,6 +1,16 @@
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2014-11-24 Michael Meissner <meissner@linux.vnet.ibm.com>
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2014-11-24 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/63965
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PR target/63965
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* config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Do not set
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Altivec & -16 mask if the type is not valid for Altivec registers.
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(rs6000_secondary_reload_memory): Add support for ((reg + const) +
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reg) that occurs during push_reload processing.
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* config/rs6000/altivec.md (altivec_mov<mode>): Add instruction
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alternative for moving constant vectors which are easy altivec
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constants to GPRs. Set the length attribute each of the
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alternatives.
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* config/rs6000/rs6000-cpus.def: Undo November 21st changes, a
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* config/rs6000/rs6000-cpus.def: Undo November 21st changes, a
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work in progress patch was committed instead of the fixes for
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work in progress patch was committed instead of the fixes for
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63965.
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63965.
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@ -189,8 +189,8 @@
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;; Vector move instructions.
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;; Vector move instructions.
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(define_insn "*altivec_mov<mode>"
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(define_insn "*altivec_mov<mode>"
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[(set (match_operand:VM2 0 "nonimmediate_operand" "=Z,v,v,*Y,*r,*r,v,v")
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[(set (match_operand:VM2 0 "nonimmediate_operand" "=Z,v,v,*Y,*r,*r,v,v,*r")
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(match_operand:VM2 1 "input_operand" "v,Z,v,r,Y,r,j,W"))]
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(match_operand:VM2 1 "input_operand" "v,Z,v,r,Y,r,j,W,W"))]
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"VECTOR_MEM_ALTIVEC_P (<MODE>mode)
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"VECTOR_MEM_ALTIVEC_P (<MODE>mode)
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&& (register_operand (operands[0], <MODE>mode)
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&& (register_operand (operands[0], <MODE>mode)
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|| register_operand (operands[1], <MODE>mode))"
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|| register_operand (operands[1], <MODE>mode))"
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@ -205,10 +205,12 @@
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case 5: return "#";
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case 5: return "#";
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case 6: return "vxor %0,%0,%0";
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case 6: return "vxor %0,%0,%0";
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case 7: return output_vec_const_move (operands);
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case 7: return output_vec_const_move (operands);
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case 8: return "#";
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default: gcc_unreachable ();
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default: gcc_unreachable ();
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}
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}
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}
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}
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[(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,vecsimple,*")])
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[(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,vecsimple,*,*")
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(set_attr "length" "4,4,4,20,20,20,4,8,32")])
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;; Unlike other altivec moves, allow the GPRs, since a normal use of TImode
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;; Unlike other altivec moves, allow the GPRs, since a normal use of TImode
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;; is for unions. However for plain data movement, slightly favor the vector
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;; is for unions. However for plain data movement, slightly favor the vector
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@ -2505,7 +2505,8 @@ rs6000_setup_reg_addr_masks (void)
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/* VMX registers can do (REG & -16) and ((REG+REG) & -16)
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/* VMX registers can do (REG & -16) and ((REG+REG) & -16)
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addressing on 128-bit types. */
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addressing on 128-bit types. */
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if (rc == RELOAD_REG_VMX && GET_MODE_SIZE (m2) == 16)
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if (rc == RELOAD_REG_VMX && GET_MODE_SIZE (m2) == 16
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&& (addr_mask & RELOAD_REG_VALID) != 0)
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addr_mask |= RELOAD_REG_AND_M16;
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addr_mask |= RELOAD_REG_AND_M16;
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reg_addr[m].addr_mask[rc] = addr_mask;
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reg_addr[m].addr_mask[rc] = addr_mask;
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@ -16652,6 +16653,17 @@ rs6000_secondary_reload_memory (rtx addr,
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}
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}
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}
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}
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/* (plus (plus (reg) (constant)) (reg)) is also generated during
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push_reload processing, so handle it now. */
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else if (GET_CODE (plus_arg0) == PLUS && REG_P (plus_arg1))
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{
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if ((addr_mask & RELOAD_REG_INDEXED) == 0)
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{
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extra_cost = 1;
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type = "indexed #2";
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}
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}
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else if (!base_reg_operand (plus_arg0, GET_MODE (plus_arg0)))
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else if (!base_reg_operand (plus_arg0, GET_MODE (plus_arg0)))
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{
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{
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fail_msg = "no base register #2";
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fail_msg = "no base register #2";
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