i386.md (fixuns_trunc<SSEMODEF>si_1): New insn.
* config/i386/i386.md (fixuns_trunc<SSEMODEF>si_1): New insn.
(fixuns_trunc<SSEMODEF>si2): Use it.
* config/i386/sse.md (vec_setv4sf_0): Export.
* config/i386/i386.c (ix86_build_const_vector): Export.
(ix86_split_convert_uns_si_sse): Rename from
ix86_expand_convert_uns_si_sse and rewrite as a splitter.
* config/i386/i386-protos.h: Update.
From-SVN: r121877
This commit is contained in:
Richard Henderson
Richard Henderson
parent
2397c5750e
commit
174c12c748
@ -1,3 +1,13 @@
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2007-02-12 Richard Henderson <rth@redhat.com>
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* config/i386/i386.md (fixuns_trunc<SSEMODEF>si_1): New insn.
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(fixuns_trunc<SSEMODEF>si2): Use it.
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* config/i386/sse.md (vec_setv4sf_0): Export.
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* config/i386/i386.c (ix86_build_const_vector): Export.
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(ix86_split_convert_uns_si_sse): Rename from
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ix86_expand_convert_uns_si_sse and rewrite as a splitter.
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* config/i386/i386-protos.h: Update.
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2007-02-13 Manuel Lopez-Ibanez <manu@gcc.gnu.org>
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PR c/29521
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@ -89,7 +89,8 @@ extern void ix86_expand_binary_operator (enum rtx_code,
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extern int ix86_binary_operator_ok (enum rtx_code, enum machine_mode, rtx[]);
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extern void ix86_expand_unary_operator (enum rtx_code, enum machine_mode,
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rtx[]);
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extern void ix86_expand_convert_uns_si_sse (rtx, rtx);
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extern rtx ix86_build_const_vector (enum machine_mode, bool, rtx);
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extern void ix86_split_convert_uns_si_sse (rtx[]);
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extern void ix86_expand_convert_uns_didf_sse (rtx, rtx);
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extern void ix86_expand_convert_uns_sidf_sse (rtx, rtx);
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extern void ix86_expand_convert_uns_sisf_sse (rtx, rtx);
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@ -1519,7 +1519,6 @@ static const char *ix86_mangle_fundamental_type (tree);
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static tree ix86_stack_protect_fail (void);
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static rtx ix86_internal_arg_pointer (void);
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static void ix86_dwarf_handle_frame_unspec (const char *, rtx, int);
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static rtx ix86_build_const_vector (enum machine_mode, bool, rtx);
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static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
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rtx, rtx, int);
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@ -9865,58 +9864,64 @@ ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
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return TRUE;
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}
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/* Convert an SF or DFmode value in an SSE register into an unsigned SImode.
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When -fpmath=387, this is done with an x87 st(0)_FP->signed-int-64
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conversion, and ignoring the upper 32 bits of the result. On x86_64,
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there is an equivalent SSE %xmm->signed-int-64 conversion.
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On x86_32, we don't have the instruction, nor the 64-bit destination
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register it requires. Do the conversion inline in the SSE registers.
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Requires SSE2. For x86_32, -mfpmath=sse, !optimize_size only. */
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/* Post-reload splitter for converting an SF or DFmode value in an
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SSE register into an unsigned SImode. */
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void
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ix86_expand_convert_uns_si_sse (rtx target, rtx input)
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ix86_split_convert_uns_si_sse (rtx operands[])
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{
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REAL_VALUE_TYPE TWO31r;
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enum machine_mode mode, vecmode;
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rtx two31, value, large, sign, result_vec, zero_or_two31, x;
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enum machine_mode vecmode;
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rtx value, large, zero_or_two31, input, two31, x;
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mode = GET_MODE (input);
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vecmode = mode == SFmode ? V4SFmode : V2DFmode;
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large = operands[1];
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zero_or_two31 = operands[2];
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input = operands[3];
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two31 = operands[4];
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vecmode = GET_MODE (large);
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value = gen_rtx_REG (vecmode, REGNO (operands[0]));
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real_ldexp (&TWO31r, &dconst1, 31);
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two31 = const_double_from_real_value (TWO31r, mode);
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two31 = ix86_build_const_vector (mode, true, two31);
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two31 = force_reg (vecmode, two31);
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/* Load up the value into the low element. We must ensure that the other
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elements are valid floats -- zero is the easiest such value. */
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if (MEM_P (input))
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{
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if (vecmode == V4SFmode)
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emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
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else
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emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
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}
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else
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{
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input = gen_rtx_REG (vecmode, REGNO (input));
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emit_move_insn (value, CONST0_RTX (vecmode));
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if (vecmode == V4SFmode)
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emit_insn (gen_sse_movss (value, value, input));
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else
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emit_insn (gen_sse2_movsd (value, value, input));
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}
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value = gen_reg_rtx (vecmode);
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ix86_expand_vector_init_one_nonzero (false, vecmode, value, input, 0);
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emit_move_insn (large, two31);
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emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
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large = gen_reg_rtx (vecmode);
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x = gen_rtx_fmt_ee (LE, vecmode, two31, value);
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x = gen_rtx_fmt_ee (LE, vecmode, large, value);
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emit_insn (gen_rtx_SET (VOIDmode, large, x));
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zero_or_two31 = gen_reg_rtx (vecmode);
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x = gen_rtx_AND (vecmode, large, two31);
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x = gen_rtx_AND (vecmode, zero_or_two31, large);
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emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
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x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
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emit_insn (gen_rtx_SET (VOIDmode, value, x));
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result_vec = gen_reg_rtx (V4SImode);
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if (mode == SFmode)
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x = gen_sse2_cvttps2dq (result_vec, value);
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large = gen_rtx_REG (V4SImode, REGNO (large));
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emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
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x = gen_rtx_REG (V4SImode, REGNO (value));
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if (vecmode == V4SFmode)
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emit_insn (gen_sse2_cvttps2dq (x, value));
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else
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x = gen_sse2_cvttpd2dq (result_vec, value);
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emit_insn (x);
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emit_insn (gen_sse2_cvttpd2dq (x, value));
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value = x;
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sign = gen_reg_rtx (V4SImode);
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emit_insn (gen_ashlv4si3 (sign, gen_lowpart (V4SImode, large),
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GEN_INT (31)));
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emit_insn (gen_xorv4si3 (result_vec, result_vec, sign));
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ix86_expand_vector_extract (false, target, result_vec, 0);
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emit_insn (gen_xorv4si3 (value, value, large));
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}
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/* Convert an unsigned DImode value into a DFmode, using only SSE.
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@ -10066,7 +10071,7 @@ ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
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then replicate the value for all elements of the vector
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register. */
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static rtx
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rtx
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ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
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{
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rtvec v;
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@ -488,6 +488,9 @@
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;; SSE asm suffix for floating point modes
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(define_mode_attr ssemodefsuffix [(SF "s") (DF "d")])
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;; SSE vector mode corresponding to a scalar mode
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(define_mode_attr ssevecmode
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[(QI "V16QI") (HI "V8HI") (SI "V4SI") (DI "V2DI") (SF "V4SF") (DF "V2DF")])
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;; Scheduling descriptions
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@ -4334,12 +4337,39 @@
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;; Unsigned conversion to SImode.
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(define_expand "fixuns_trunc<mode>si2"
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[(set (match_operand:SI 0 "nonimmediate_operand" "")
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(fix:SI (match_operand:SSEMODEF 1 "register_operand" "")))]
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"!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH
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&& TARGET_KEEPS_VECTOR_ALIGNED_STACK && !optimize_size"
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[(parallel
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[(set (match_operand:SI 0 "register_operand" "")
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(unsigned_fix:SI
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(match_operand:SSEMODEF 1 "nonimmediate_operand" "")))
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(use (match_dup 2))
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(clobber (match_scratch:<ssevecmode> 3 ""))
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(clobber (match_scratch:<ssevecmode> 4 ""))])]
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"!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH && !optimize_size"
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{
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ix86_expand_convert_uns_si_sse (operands[0], operands[1]);
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enum machine_mode mode = <MODE>mode;
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enum machine_mode vecmode = <ssevecmode>mode;
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REAL_VALUE_TYPE TWO31r;
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rtx two31;
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real_ldexp (&TWO31r, &dconst1, 31);
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two31 = const_double_from_real_value (TWO31r, mode);
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two31 = ix86_build_const_vector (mode, true, two31);
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operands[2] = force_reg (vecmode, two31);
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})
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(define_insn_and_split "*fixuns_trunc<mode>_1"
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[(set (match_operand:SI 0 "register_operand" "=&x,&x")
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(unsigned_fix:SI
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(match_operand:SSEMODEF 3 "nonimmediate_operand" "xm,xm")))
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(use (match_operand:<ssevecmode> 4 "nonimmediate_operand" "m,x"))
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(clobber (match_scratch:<ssevecmode> 1 "=x,&x"))
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(clobber (match_scratch:<ssevecmode> 2 "=x,x"))]
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"!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH && !optimize_size"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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ix86_split_convert_uns_si_sse (operands);
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DONE;
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})
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@ -1367,7 +1367,7 @@
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DONE;
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})
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(define_insn "*vec_setv4sf_0"
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(define_insn "vec_setv4sf_0"
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[(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,Y2,m")
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(vec_merge:V4SF
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(vec_duplicate:V4SF
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