arm.c (arm_option_override): Reoganized and split into : (arm_option_params_internal); New function.
2014-09-23 Christian Bruel <christian.bruel@st.com> * config/arm/arm.c (arm_option_override): Reoganized and split into : (arm_option_params_internal); New function. (arm_option_check_internal): New function. (arm_option_override_internal): New function. (thumb_code, thumb1_code): Remove. * config/arm/arm.h (TREE_TARGET_THUMB, TREE_TARGET_THUMB1): New macros. (TREE_TARGET_THUM2, TREE_TARGET_ARM): Likewise. (thumb_code, thumb1_code): Remove. * config/arm/arm.md (is_thumb, is_thumb1): Check TARGET flag. From-SVN: r222995
This commit is contained in:
Christian Bruel
Christian Bruel
parent
c37aa43b98
commit
1a7ae4cef7
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@ -1,3 +1,15 @@
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2014-09-23 Christian Bruel <christian.bruel@st.com>
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* config/arm/arm.c (arm_option_override): Reoganized and split into :
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(arm_option_params_internal); New function.
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(arm_option_check_internal): New function.
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(arm_option_override_internal): New function.
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(thumb_code, thumb1_code): Remove.
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* config/arm/arm.h (TREE_TARGET_THUMB, TREE_TARGET_THUMB1): New macros.
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(TREE_TARGET_THUM2, TREE_TARGET_ARM): Likewise.
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(thumb_code, thumb1_code): Remove.
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* config/arm/arm.md (is_thumb, is_thumb1): Check TARGET flag.
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2015-05-11 Uros Bizjak <ubizjak@gmail.com>
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* config/alpha/alpha.c (alpha_emit_set_const_1)
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@ -846,12 +846,6 @@ int arm_tune_wbuf = 0;
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/* Nonzero if tuning for Cortex-A9. */
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int arm_tune_cortex_a9 = 0;
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/* Nonzero if generating Thumb instructions. */
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int thumb_code = 0;
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/* Nonzero if generating Thumb-1 instructions. */
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int thumb1_code = 0;
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/* Nonzero if we should define __THUMB_INTERWORK__ in the
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preprocessor.
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XXX This is a bit of a hack, it's intended to help work around
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@ -2669,6 +2663,150 @@ arm_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
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return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
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}
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/* Check any incompatible options that the user has specified. */
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static void
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arm_option_check_internal (struct gcc_options *opts)
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{
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/* Make sure that the processor choice does not conflict with any of the
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other command line choices. */
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if (TREE_TARGET_ARM (opts) && !(insn_flags & FL_NOTM))
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error ("target CPU does not support ARM mode");
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/* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
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from here where no function is being compiled currently. */
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if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TREE_TARGET_ARM (opts))
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warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
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if (TREE_TARGET_ARM (opts) && TARGET_CALLEE_INTERWORKING)
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warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
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/* If this target is normally configured to use APCS frames, warn if they
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are turned off and debugging is turned on. */
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if (TREE_TARGET_ARM (opts)
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&& write_symbols != NO_DEBUG
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&& !TARGET_APCS_FRAME
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&& (TARGET_DEFAULT & MASK_APCS_FRAME))
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warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
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/* iWMMXt unsupported under Thumb mode. */
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if (TREE_TARGET_THUMB (opts) && TARGET_IWMMXT)
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error ("iWMMXt unsupported under Thumb mode");
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if (TARGET_HARD_TP && TREE_TARGET_THUMB1 (opts))
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error ("can not use -mtp=cp15 with 16-bit Thumb");
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if (TREE_TARGET_THUMB (opts) && TARGET_VXWORKS_RTP && flag_pic)
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{
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error ("RTP PIC is incompatible with Thumb");
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flag_pic = 0;
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}
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/* We only support -mslow-flash-data on armv7-m targets. */
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if (target_slow_flash_data
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&& ((!(arm_arch7 && !arm_arch_notm) && !arm_arch7em)
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|| (TREE_TARGET_THUMB1 (opts) || flag_pic || TARGET_NEON)))
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error ("-mslow-flash-data only supports non-pic code on armv7-m targets");
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}
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/* Set params depending on attributes and optimization options. */
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static void
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arm_option_params_internal (struct gcc_options *opts)
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{
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/* If we are not using the default (ARM mode) section anchor offset
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ranges, then set the correct ranges now. */
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if (TREE_TARGET_THUMB1 (opts))
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{
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/* Thumb-1 LDR instructions cannot have negative offsets.
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Permissible positive offset ranges are 5-bit (for byte loads),
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6-bit (for halfword loads), or 7-bit (for word loads).
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Empirical results suggest a 7-bit anchor range gives the best
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overall code size. */
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targetm.min_anchor_offset = 0;
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targetm.max_anchor_offset = 127;
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}
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else if (TREE_TARGET_THUMB2 (opts))
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{
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/* The minimum is set such that the total size of the block
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for a particular anchor is 248 + 1 + 4095 bytes, which is
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divisible by eight, ensuring natural spacing of anchors. */
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targetm.min_anchor_offset = -248;
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targetm.max_anchor_offset = 4095;
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}
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else
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{
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targetm.min_anchor_offset = TARGET_MIN_ANCHOR_OFFSET;
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targetm.max_anchor_offset = TARGET_MAX_ANCHOR_OFFSET;
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}
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if (optimize_size)
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{
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/* If optimizing for size, bump the number of instructions that we
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are prepared to conditionally execute (even on a StrongARM). */
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max_insns_skipped = 6;
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/* For THUMB2, we limit the conditional sequence to one IT block. */
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if (TREE_TARGET_THUMB2 (opts))
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max_insns_skipped = opts->x_arm_restrict_it ? 1 : 4;
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}
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else
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max_insns_skipped = current_tune->max_insns_skipped;
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}
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/* Reset options between modes that the user has specified. */
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static void
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arm_option_override_internal (struct gcc_options *opts,
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struct gcc_options *opts_set)
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{
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if (TREE_TARGET_THUMB (opts) && !(insn_flags & FL_THUMB))
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{
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warning (0, "target CPU does not support THUMB instructions");
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opts->x_target_flags &= ~MASK_THUMB;
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}
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if (TARGET_APCS_FRAME && TREE_TARGET_THUMB (opts))
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{
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/* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
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opts->x_target_flags &= ~MASK_APCS_FRAME;
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}
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/* Callee super interworking implies thumb interworking. Adding
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this to the flags here simplifies the logic elsewhere. */
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if (TREE_TARGET_THUMB (opts) && TARGET_CALLEE_INTERWORKING)
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opts->x_target_flags |= MASK_INTERWORK;
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if (! opts_set->x_arm_restrict_it)
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opts->x_arm_restrict_it = arm_arch8;
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if (!TREE_TARGET_THUMB2 (opts))
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opts->x_arm_restrict_it = 0;
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if (TREE_TARGET_THUMB1 (opts))
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{
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/* Don't warn since it's on by default in -O2. */
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opts->x_flag_schedule_insns = 0;
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}
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/* Disable shrink-wrap when optimizing function for size, since it tends to
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generate additional returns. */
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if (optimize_function_for_size_p (cfun) && TREE_TARGET_THUMB2 (opts))
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opts->x_flag_shrink_wrap = false;
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/* In Thumb1 mode, we emit the epilogue in RTL, but the last insn
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- epilogue_insns - does not accurately model the corresponding insns
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emitted in the asm file. In particular, see the comment in thumb_exit
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'Find out how many of the (return) argument registers we can corrupt'.
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As a consequence, the epilogue may clobber registers without fipa-ra
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finding out about it. Therefore, disable fipa-ra in Thumb1 mode.
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TODO: Accurately model clobbers for epilogue_insns and reenable
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fipa-ra. */
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if (TREE_TARGET_THUMB1 (opts))
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opts->x_flag_ipa_ra = 0;
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/* Thumb2 inline assembly code should always use unified syntax.
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This will apply to ARM and Thumb1 eventually. */
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opts->x_inline_asm_unified = TREE_TARGET_THUMB2 (opts);
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}
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/* Fix up any incompatible options that the user has specified. */
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static void
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arm_option_override (void)
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@ -2815,10 +2953,9 @@ arm_option_override (void)
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tune_flags = arm_selected_tune->flags;
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current_tune = arm_selected_tune->tune;
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/* Make sure that the processor choice does not conflict with any of the
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other command line choices. */
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if (TARGET_ARM && !(insn_flags & FL_NOTM))
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error ("target CPU does not support ARM mode");
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/* TBD: Dwarf info for apcs frame is not handled yet. */
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if (TARGET_APCS_FRAME)
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flag_shrink_wrap = false;
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/* BPABI targets use linker tricks to allow interworking on cores
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without thumb support. */
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@ -2828,31 +2965,6 @@ arm_option_override (void)
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target_flags &= ~MASK_INTERWORK;
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}
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if (TARGET_THUMB && !(insn_flags & FL_THUMB))
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{
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warning (0, "target CPU does not support THUMB instructions");
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target_flags &= ~MASK_THUMB;
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}
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if (TARGET_APCS_FRAME && TARGET_THUMB)
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{
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/* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
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target_flags &= ~MASK_APCS_FRAME;
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}
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/* Callee super interworking implies thumb interworking. Adding
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this to the flags here simplifies the logic elsewhere. */
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if (TARGET_THUMB && TARGET_CALLEE_INTERWORKING)
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target_flags |= MASK_INTERWORK;
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/* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
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from here where no function is being compiled currently. */
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if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM)
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warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
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if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
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warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
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if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
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{
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warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
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@ -2868,14 +2980,6 @@ arm_option_override (void)
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if (TARGET_APCS_REENT)
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warning (0, "APCS reentrant code not supported. Ignored");
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/* If this target is normally configured to use APCS frames, warn if they
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are turned off and debugging is turned on. */
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if (TARGET_ARM
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&& write_symbols != NO_DEBUG
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&& !TARGET_APCS_FRAME
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&& (TARGET_DEFAULT & MASK_APCS_FRAME))
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warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
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if (TARGET_APCS_FLOAT)
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warning (0, "passing floating point arguments in fp regs not yet supported");
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@ -2897,8 +3001,6 @@ arm_option_override (void)
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arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
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arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
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thumb_code = TARGET_ARM == 0;
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thumb1_code = TARGET_THUMB1 != 0;
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arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
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arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
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arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
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@ -2909,32 +3011,6 @@ arm_option_override (void)
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arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0;
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arm_arch_crc = (insn_flags & FL_CRC32) != 0;
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arm_m_profile_small_mul = (insn_flags & FL_SMALLMUL) != 0;
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if (arm_restrict_it == 2)
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arm_restrict_it = arm_arch8 && TARGET_THUMB2;
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if (!TARGET_THUMB2)
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arm_restrict_it = 0;
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/* If we are not using the default (ARM mode) section anchor offset
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ranges, then set the correct ranges now. */
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if (TARGET_THUMB1)
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{
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/* Thumb-1 LDR instructions cannot have negative offsets.
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Permissible positive offset ranges are 5-bit (for byte loads),
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6-bit (for halfword loads), or 7-bit (for word loads).
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Empirical results suggest a 7-bit anchor range gives the best
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overall code size. */
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targetm.min_anchor_offset = 0;
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targetm.max_anchor_offset = 127;
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}
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else if (TARGET_THUMB2)
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{
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/* The minimum is set such that the total size of the block
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for a particular anchor is 248 + 1 + 4095 bytes, which is
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divisible by eight, ensuring natural spacing of anchors. */
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targetm.min_anchor_offset = -248;
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targetm.max_anchor_offset = 4095;
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}
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/* V5 code we generate is completely interworking capable, so we turn off
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TARGET_INTERWORK here to avoid many tests later on. */
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@ -2994,10 +3070,6 @@ arm_option_override (void)
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if (TARGET_IWMMXT && TARGET_NEON)
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error ("iWMMXt and NEON are incompatible");
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/* iWMMXt unsupported under Thumb mode. */
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if (TARGET_THUMB && TARGET_IWMMXT)
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error ("iWMMXt unsupported under Thumb mode");
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/* __fp16 support currently assumes the core has ldrh. */
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if (!arm_arch4 && arm_fp16_format != ARM_FP16_FORMAT_NONE)
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sorry ("__fp16 and no ldrh");
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@ -3042,9 +3114,6 @@ arm_option_override (void)
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target_thread_pointer = TP_SOFT;
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}
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if (TARGET_HARD_TP && TARGET_THUMB1)
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error ("can not use -mtp=cp15 with 16-bit Thumb");
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/* Override the default structure alignment for AAPCS ABI. */
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if (!global_options_set.x_arm_structure_size_boundary)
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{
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@ -3067,12 +3136,6 @@ arm_option_override (void)
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}
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}
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if (!TARGET_ARM && TARGET_VXWORKS_RTP && flag_pic)
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{
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error ("RTP PIC is incompatible with Thumb");
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flag_pic = 0;
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}
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/* If stack checking is disabled, we can use r10 as the PIC register,
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which keeps r9 available. The EABI specifies r9 as the PIC register. */
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if (flag_pic && TARGET_SINGLE_PIC_BASE)
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@ -3140,25 +3203,6 @@ arm_option_override (void)
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unaligned_access = 0;
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}
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if (TARGET_THUMB1 && flag_schedule_insns)
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{
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/* Don't warn since it's on by default in -O2. */
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flag_schedule_insns = 0;
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}
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if (optimize_size)
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{
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/* If optimizing for size, bump the number of instructions that we
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are prepared to conditionally execute (even on a StrongARM). */
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max_insns_skipped = 6;
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/* For THUMB2, we limit the conditional sequence to one IT block. */
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if (TARGET_THUMB2)
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max_insns_skipped = MAX_INSN_PER_IT_BLOCK;
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}
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else
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max_insns_skipped = current_tune->max_insns_skipped;
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/* Hot/Cold partitioning is not currently supported, since we can't
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handle literal pool placement in that case. */
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if (flag_reorder_blocks_and_partition)
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@ -3236,45 +3280,19 @@ arm_option_override (void)
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global_options.x_param_values,
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global_options_set.x_param_values);
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/* Disable shrink-wrap when optimizing function for size, since it tends to
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generate additional returns. */
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if (optimize_function_for_size_p (cfun) && TARGET_THUMB2)
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flag_shrink_wrap = false;
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/* TBD: Dwarf info for apcs frame is not handled yet. */
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if (TARGET_APCS_FRAME)
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flag_shrink_wrap = false;
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/* We only support -mslow-flash-data on armv7-m targets. */
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if (target_slow_flash_data
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&& ((!(arm_arch7 && !arm_arch_notm) && !arm_arch7em)
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|| (TARGET_THUMB1 || flag_pic || TARGET_NEON)))
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error ("-mslow-flash-data only supports non-pic code on armv7-m targets");
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/* Currently, for slow flash data, we just disable literal pools. */
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if (target_slow_flash_data)
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arm_disable_literal_pool = true;
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/* Thumb2 inline assembly code should always use unified syntax.
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This will apply to ARM and Thumb1 eventually. */
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if (TARGET_THUMB2)
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inline_asm_unified = 1;
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/* Disable scheduling fusion by default if it's not armv7 processor
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or doesn't prefer ldrd/strd. */
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if (flag_schedule_fusion == 2
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&& (!arm_arch7 || !current_tune->prefer_ldrd_strd))
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flag_schedule_fusion = 0;
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|
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/* In Thumb1 mode, we emit the epilogue in RTL, but the last insn
|
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- epilogue_insns - does not accurately model the corresponding insns
|
||||
emitted in the asm file. In particular, see the comment in thumb_exit
|
||||
'Find out how many of the (return) argument registers we can corrupt'.
|
||||
As a consequence, the epilogue may clobber registers without fipa-ra
|
||||
finding out about it. Therefore, disable fipa-ra in Thumb1 mode.
|
||||
TODO: Accurately model clobbers for epilogue_insns and reenable
|
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fipa-ra. */
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if (TARGET_THUMB1)
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flag_ipa_ra = 0;
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arm_option_override_internal (&global_options, &global_options_set);
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arm_option_check_internal (&global_options);
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arm_option_params_internal (&global_options);
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/* Register global variables with the garbage collector. */
|
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arm_add_gc_roots ();
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|
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@ -252,6 +252,13 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
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#define SUBTARGET_CPP_SPEC ""
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#endif
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/* Tree Target Specification. */
|
||||
#define TREE_TARGET_THUMB(opts) (TARGET_THUMB_P (opts->x_target_flags))
|
||||
#define TREE_TARGET_ARM(opts) (!TARGET_THUMB_P (opts->x_target_flags))
|
||||
#define TREE_TARGET_THUMB1(opts) (TARGET_THUMB_P (opts->x_target_flags) \
|
||||
&& !arm_arch_thumb2)
|
||||
#define TREE_TARGET_THUMB2(opts) (TARGET_THUMB_P (opts->x_target_flags) \
|
||||
&& arm_arch_thumb2)
|
||||
/* Run-time Target Specification. */
|
||||
#define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
|
||||
/* Use hardware floating point instructions. */
|
||||
|
|
@ -528,12 +535,6 @@ extern int arm_arch8;
|
|||
/* Nonzero if this chip can benefit from load scheduling. */
|
||||
extern int arm_ld_sched;
|
||||
|
||||
/* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */
|
||||
extern int thumb_code;
|
||||
|
||||
/* Nonzero if generating Thumb-1 code. */
|
||||
extern int thumb1_code;
|
||||
|
||||
/* Nonzero if this chip is a StrongARM. */
|
||||
extern int arm_tune_strongarm;
|
||||
|
||||
|
|
|
|||
|
|
@ -69,13 +69,17 @@
|
|||
; IS_THUMB is set to 'yes' when we are generating Thumb code, and 'no' when
|
||||
; generating ARM code. This is used to control the length of some insn
|
||||
; patterns that share the same RTL in both ARM and Thumb code.
|
||||
(define_attr "is_thumb" "no,yes" (const (symbol_ref "thumb_code")))
|
||||
(define_attr "is_thumb" "yes,no"
|
||||
(const (if_then_else (symbol_ref "TARGET_THUMB")
|
||||
(const_string "yes") (const_string "no"))))
|
||||
|
||||
; IS_ARCH6 is set to 'yes' when we are generating code form ARMv6.
|
||||
(define_attr "is_arch6" "no,yes" (const (symbol_ref "arm_arch6")))
|
||||
|
||||
; IS_THUMB1 is set to 'yes' iff we are generating Thumb-1 code.
|
||||
(define_attr "is_thumb1" "no,yes" (const (symbol_ref "thumb1_code")))
|
||||
(define_attr "is_thumb1" "yes,no"
|
||||
(const (if_then_else (symbol_ref "TARGET_THUMB1")
|
||||
(const_string "yes") (const_string "no"))))
|
||||
|
||||
; We use this attribute to disable alternatives that can produce 32-bit
|
||||
; instructions inside an IT-block in Thumb2 state. ARMv8 deprecates IT blocks
|
||||
|
|
|
|||
Loading…
Reference in New Issue