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[Aarch64, Patch] Update failing testcase pr62178.c

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This patch changes pr62178.c so that it now scans
for two `ldr`s, one into an `s` register, instead
of a `ld1r` as before. Also add a scan for an mla
instruction.

The `ld1r` was needed when this should have generated
a mla by vector. Now that we can generate an mla by
element instruction and can load directly into the
simd register, it is cheaper to not do the ld1r
which needlessly duplicates the single element used
across the whole vector register.

Committed on behalf of Jackson Woodruff

gcc/testsuite/

	* gcc.target/aarch64/pr62178.c: Updated testcase
	to scan for two ldrs and an mla.

From-SVN: r252086
This commit is contained in:
Jackson Woodruff 2017-09-13 14:08:49 +00:00 committed by James Greenhalgh
parent d0dda80415
commit 1cb656f82c
2 changed files with 8 additions and 1 deletions
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5
gcc/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2017-09-13 Jackson Woodruff <jackson.woodruff@arm.com>
* gcc.target/aarch64/pr62178.c: Updated testcase
to scan for two ldrs and an mla.
2017-09-13 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/59949

4
gcc/testsuite/gcc.target/aarch64/pr62178.c
View File

@ -14,4 +14,6 @@ void foo (void) {
}
}
/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\."} } */
/* { dg-final { scan-assembler "ldr\\ts\[0-9\]+, \\\[x\[0-9\]+, \[0-9\]+\\\]!" } } */
/* { dg-final { scan-assembler "ldr\\tq\[0-9\]+, \\\[x\[0-9\]+\\\], \[0-9\]+" } } */
/* { dg-final { scan-assembler "mla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[0\\\]" } } */