[AArch64_BE 3/4] Big-Endian lane numbering fix
2014-01-23 James Greenhalgh <james.greenhalgh@arm.com> * config/aarch64/aarch64-simd.md (aarch64_dup_lane<mode>): Correct lane number on big-endian. (aarch64_dup_lane_<vswap_widthi_name><mode>): Likewise. (*aarch64_mul3_elt<mode>): Likewise. (*aarch64_mul3_elt<vswap_width_name><mode>): Likewise. (*aarch64_mul3_elt_to_64v2df): Likewise. (*aarch64_mla_elt<mode>): Likewise. (*aarch64_mla_elt_<vswap_width_name><mode>): Likewise. (*aarch64_mls_elt<mode>): Likewise. (*aarch64_mls_elt_<vswap_width_name><mode>): Likewise. (*aarch64_fma4_elt<mode>): Likewise. (*aarch64_fma4_elt_<vswap_width_name><mode>): Likewise. (*aarch64_fma4_elt_to_64v2df): Likewise. (*aarch64_fnma4_elt<mode>): Likewise. (*aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise. (*aarch64_fnma4_elt_to_64v2df): Likewise. (aarch64_sq<r>dmulh_lane<mode>): Likewise. (aarch64_sq<r>dmulh_laneq<mode>): Likewise. (aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal): Likewise. (aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal): Likewise. (aarch64_sqdml<SBINQOPS:as>l2_lane<mode>_internal): Likewise. (aarch64_sqdmull_lane<mode>_internal): Likewise. (aarch64_sqdmull2_lane<mode>_internal): Likewise. From-SVN: r206972
This commit is contained in:
James Greenhalgh
Kyrylo Tkachov
parent
dafb9b6489
commit
1dd055a27d
@ -1,3 +1,29 @@
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2014-01-23 James Greenhalgh <james.greenhalgh@arm.com>
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* config/aarch64/aarch64-simd.md
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(aarch64_dup_lane<mode>): Correct lane number on big-endian.
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(aarch64_dup_lane_<vswap_widthi_name><mode>): Likewise.
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(*aarch64_mul3_elt<mode>): Likewise.
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(*aarch64_mul3_elt<vswap_width_name><mode>): Likewise.
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(*aarch64_mul3_elt_to_64v2df): Likewise.
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(*aarch64_mla_elt<mode>): Likewise.
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(*aarch64_mla_elt_<vswap_width_name><mode>): Likewise.
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(*aarch64_mls_elt<mode>): Likewise.
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(*aarch64_mls_elt_<vswap_width_name><mode>): Likewise.
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(*aarch64_fma4_elt<mode>): Likewise.
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(*aarch64_fma4_elt_<vswap_width_name><mode>): Likewise.
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(*aarch64_fma4_elt_to_64v2df): Likewise.
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(*aarch64_fnma4_elt<mode>): Likewise.
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(*aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
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(*aarch64_fnma4_elt_to_64v2df): Likewise.
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(aarch64_sq<r>dmulh_lane<mode>): Likewise.
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(aarch64_sq<r>dmulh_laneq<mode>): Likewise.
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(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal): Likewise.
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(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal): Likewise.
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(aarch64_sqdml<SBINQOPS:as>l2_lane<mode>_internal): Likewise.
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(aarch64_sqdmull_lane<mode>_internal): Likewise.
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(aarch64_sqdmull2_lane<mode>_internal): Likewise.
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2013-01-23 Alex Velenko <Alex.Velenko@arm.com>
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* config/aarch64/aarch64-simd.md
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@ -67,7 +67,10 @@
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(parallel [(match_operand:SI 2 "immediate_operand" "i")])
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)))]
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"TARGET_SIMD"
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"dup\\t%0.<Vtype>, %1.<Vetype>[%2]"
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{
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operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
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return "dup\\t%0.<Vtype>, %1.<Vetype>[%2]";
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}
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[(set_attr "type" "neon_dup<q>")]
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)
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@ -79,7 +82,11 @@
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(parallel [(match_operand:SI 2 "immediate_operand" "i")])
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)))]
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"TARGET_SIMD"
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"dup\\t%0.<Vtype>, %1.<Vetype>[%2]"
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{
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operands[2] = GEN_INT (ENDIAN_LANE_N (<VSWAP_WIDTH>mode,
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INTVAL (operands[2])));
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return "dup\\t%0.<Vtype>, %1.<Vetype>[%2]";
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}
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[(set_attr "type" "neon_dup<q>")]
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)
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@ -288,7 +295,10 @@
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(parallel [(match_operand:SI 2 "immediate_operand")])))
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(match_operand:VMUL 3 "register_operand" "w")))]
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"TARGET_SIMD"
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"<f>mul\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]"
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{
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operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
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return "<f>mul\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
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}
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[(set_attr "type" "neon<fp>_mul_<Vetype>_scalar<q>")]
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)
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@ -301,7 +311,11 @@
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(parallel [(match_operand:SI 2 "immediate_operand")])))
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(match_operand:VMUL_CHANGE_NLANES 3 "register_operand" "w")))]
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"TARGET_SIMD"
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"<f>mul\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]"
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{
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operands[2] = GEN_INT (ENDIAN_LANE_N (<VSWAP_WIDTH>mode,
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INTVAL (operands[2])));
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return "<f>mul\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
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}
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[(set_attr "type" "neon<fp>_mul_<Vetype>_scalar<q>")]
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)
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@ -324,7 +338,10 @@
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(parallel [(match_operand:SI 2 "immediate_operand")]))
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(match_operand:DF 3 "register_operand" "w")))]
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"TARGET_SIMD"
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"fmul\\t%0.2d, %3.2d, %1.d[%2]"
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{
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operands[2] = GEN_INT (ENDIAN_LANE_N (V2DFmode, INTVAL (operands[2])));
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return "fmul\\t%0.2d, %3.2d, %1.d[%2]";
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}
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[(set_attr "type" "neon_fp_mul_d_scalar_q")]
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)
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@ -783,7 +800,10 @@
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(match_operand:VDQHS 3 "register_operand" "w"))
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(match_operand:VDQHS 4 "register_operand" "0")))]
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"TARGET_SIMD"
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"mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
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{
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operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
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return "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
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}
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[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
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)
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@ -798,7 +818,11 @@
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(match_operand:VDQHS 3 "register_operand" "w"))
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(match_operand:VDQHS 4 "register_operand" "0")))]
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"TARGET_SIMD"
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"mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
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{
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operands[2] = GEN_INT (ENDIAN_LANE_N (<VSWAP_WIDTH>mode,
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INTVAL (operands[2])));
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return "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
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}
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[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
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)
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@ -823,7 +847,10 @@
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(parallel [(match_operand:SI 2 "immediate_operand")])))
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(match_operand:VDQHS 3 "register_operand" "w"))))]
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"TARGET_SIMD"
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"mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
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{
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operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
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return "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
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}
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[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
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)
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@ -838,7 +865,11 @@
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(parallel [(match_operand:SI 2 "immediate_operand")])))
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(match_operand:VDQHS 3 "register_operand" "w"))))]
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"TARGET_SIMD"
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"mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
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{
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operands[2] = GEN_INT (ENDIAN_LANE_N (<VSWAP_WIDTH>mode,
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INTVAL (operands[2])));
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return "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
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}
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[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
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)
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@ -1237,7 +1268,10 @@
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(match_operand:VDQF 3 "register_operand" "w")
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(match_operand:VDQF 4 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
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{
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operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
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return "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
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}
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[(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
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)
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@ -1251,7 +1285,11 @@
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(match_operand:VDQSF 3 "register_operand" "w")
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(match_operand:VDQSF 4 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
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{
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operands[2] = GEN_INT (ENDIAN_LANE_N (<VSWAP_WIDTH>mode,
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INTVAL (operands[2])));
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return "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
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}
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[(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
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)
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@ -1276,7 +1314,10 @@
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(match_operand:DF 3 "register_operand" "w")
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(match_operand:DF 4 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmla\\t%0.2d, %3.2d, %1.2d[%2]"
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{
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operands[2] = GEN_INT (ENDIAN_LANE_N (V2DFmode, INTVAL (operands[2])));
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return "fmla\\t%0.2d, %3.2d, %1.2d[%2]";
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}
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[(set_attr "type" "neon_fp_mla_d_scalar_q")]
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)
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@ -1303,7 +1344,10 @@
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(parallel [(match_operand:SI 2 "immediate_operand")])))
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(match_operand:VDQF 4 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
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{
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operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
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return "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
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}
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[(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
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)
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@ -1318,7 +1362,11 @@
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(parallel [(match_operand:SI 2 "immediate_operand")])))
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(match_operand:VDQSF 4 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
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{
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operands[2] = GEN_INT (ENDIAN_LANE_N (<VSWAP_WIDTH>mode,
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INTVAL (operands[2])));
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return "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
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}
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[(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
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)
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@ -1345,7 +1393,10 @@
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(match_operand:DF 3 "register_operand" "w"))
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(match_operand:DF 4 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmls\\t%0.2d, %3.2d, %1.2d[%2]"
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{
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operands[2] = GEN_INT (ENDIAN_LANE_N (V2DFmode, INTVAL (operands[2])));
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return "fmls\\t%0.2d, %3.2d, %1.2d[%2]";
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}
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[(set_attr "type" "neon_fp_mla_d_scalar_q")]
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)
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@ -2542,6 +2593,7 @@
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"TARGET_SIMD"
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"*
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aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCOND>mode));
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operands[3] = GEN_INT (ENDIAN_LANE_N (<VCOND>mode, INTVAL (operands[3])));
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return \"sq<r>dmulh\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%3]\";"
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[(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
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)
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@ -2557,6 +2609,7 @@
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"TARGET_SIMD"
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"*
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aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode));
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operands[3] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[3])));
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return \"sq<r>dmulh\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%3]\";"
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[(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
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)
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@ -2572,6 +2625,7 @@
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"TARGET_SIMD"
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"*
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aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode));
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operands[3] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[3])));
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return \"sq<r>dmulh\\t%<v>0, %<v>1, %2.<v>[%3]\";"
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[(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
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)
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@ -2612,7 +2666,11 @@
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))
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(const_int 1))))]
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"TARGET_SIMD"
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"sqdml<SBINQOPS:as>l\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]"
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{
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operands[4] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[4])));
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return
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"sqdml<SBINQOPS:as>l\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
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}
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[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
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)
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@ -2631,7 +2689,11 @@
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)
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(const_int 1))))]
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"TARGET_SIMD"
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"sqdml<SBINQOPS:as>l\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]"
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{
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operands[4] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[4])));
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return
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"sqdml<SBINQOPS:as>l\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
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}
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[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
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)
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@ -2782,7 +2844,11 @@
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))))
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(const_int 1))))]
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"TARGET_SIMD"
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"sqdml<SBINQOPS:as>l2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]"
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{
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operands[4] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[4])));
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return
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"sqdml<SBINQOPS:as>l2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
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}
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[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
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)
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@ -2929,7 +2995,10 @@
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))
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(const_int 1)))]
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"TARGET_SIMD"
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"sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]"
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{
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operands[3] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[3])));
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return "sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]";
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}
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[(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
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)
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@ -2946,7 +3015,10 @@
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))
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(const_int 1)))]
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"TARGET_SIMD"
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"sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]"
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{
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operands[3] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[3])));
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return "sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]";
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}
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[(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
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)
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@ -3047,7 +3119,10 @@
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))
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(const_int 1)))]
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"TARGET_SIMD"
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"sqdmull2\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]"
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{
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operands[3] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[3])));
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return "sqdmull2\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]";
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}
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[(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
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)
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