[ARM] Implement support for ACLE Coprocessor LDC and STC intrinsics
gcc/ChangeLog: 2017-01-06 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/arm/arm.md (*ldc): New. (*stc): New. (<ldc>): New. (<stc>): New. * config/arm/arm.c (arm_coproc_builtin_available): Add support for ldc,ldcl,stc,stcl,ldc2,ldc2l,stc2 and stc2l. (arm_coproc_ldc_stc_legitimate_address): New. * config/arm/arm-builtins.c (arm_type_qualifiers): Add 'qualifier_const_pointer'. (LDC_QUALIFIERS): Define to... (arm_ldc_qualifiers): ... this. New. (STC_QUALIFIERS): Define to... (arm_stc_qualifiers): ... this. New. * config/arm/arm-protos.h (arm_coproc_ldc_stc_legitimate_address): New. * config/arm/arm_acle.h (__arm_ldc, __arm_ldcl, __arm_stc, __arm_stcl, __arm_ldc2, __arm_ldc2l, __arm_stc2, __arm_stc2l): New. * config/arm/arm_acle_builtins.def (ldc, ldc2, ldcl, ldc2l, stc, stc2, stcl, stc2l): New. * config/arm/constraints.md (Uz): New. * config/arm/iterators.md (LDCI, STCI, ldc, stc, LDC STC): New. * config/arm/unspecs.md (VUNSPEC_LDC, VUNSPEC_LDC2, VUNSPEC_LDCL, VUNSPEC_LDC2L, VUNSPEC_STC, VUNSPEC_STC2, VUNSPEC_STCL, VUNSPEC_STC2L): New. gcc/testsuite/ChangeLog: 2017-01-06 Andre Vieira <andre.simoesdiasvieira@arm.com> * gcc.target/arm/acle/ldc: New. * gcc.target/arm/acle/ldc2: New. * gcc.target/arm/acle/ldcl: New. * gcc.target/arm/acle/ldc2l: New. * gcc.target/arm/acle/stc: New. * gcc.target/arm/acle/stc2: New. * gcc.target/arm/acle/stcl: New. * gcc.target/arm/acle/stc2l: New. From-SVN: r244173
This commit is contained in:
Andre Vieira
Andre Vieira
parent
d57daa0c9d
commit
3811581f8b
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@ -1,3 +1,30 @@
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2017-01-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/arm/arm.md (*ldc): New.
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(*stc): New.
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(<ldc>): New.
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(<stc>): New.
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* config/arm/arm.c (arm_coproc_builtin_available): Add
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support for ldc,ldcl,stc,stcl,ldc2,ldc2l,stc2 and stc2l.
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(arm_coproc_ldc_stc_legitimate_address): New.
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* config/arm/arm-builtins.c (arm_type_qualifiers): Add
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'qualifier_const_pointer'.
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(LDC_QUALIFIERS): Define to...
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(arm_ldc_qualifiers): ... this. New.
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(STC_QUALIFIERS): Define to...
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(arm_stc_qualifiers): ... this. New.
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* config/arm/arm-protos.h
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(arm_coproc_ldc_stc_legitimate_address): New.
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* config/arm/arm_acle.h (__arm_ldc, __arm_ldcl, __arm_stc,
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__arm_stcl, __arm_ldc2, __arm_ldc2l, __arm_stc2, __arm_stc2l): New.
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* config/arm/arm_acle_builtins.def (ldc, ldc2, ldcl, ldc2l, stc,
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stc2, stcl, stc2l): New.
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* config/arm/constraints.md (Uz): New.
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* config/arm/iterators.md (LDCI, STCI, ldc, stc, LDC STC): New.
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* config/arm/unspecs.md (VUNSPEC_LDC, VUNSPEC_LDC2, VUNSPEC_LDCL,
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VUNSPEC_LDC2L, VUNSPEC_STC, VUNSPEC_STC2, VUNSPEC_STCL,
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VUNSPEC_STC2L): New.
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2017-01-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/arm/arm.md (<cdp>): New.
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@ -51,6 +51,8 @@ enum arm_type_qualifiers
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qualifier_const = 0x2, /* 1 << 1 */
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/* T *foo. */
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qualifier_pointer = 0x4, /* 1 << 2 */
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/* const T * foo. */
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qualifier_const_pointer = 0x6,
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/* Used when expanding arguments if an operand could
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be an immediate. */
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qualifier_immediate = 0x8, /* 1 << 3 */
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@ -178,6 +180,23 @@ arm_cdp_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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qualifier_unsigned_immediate };
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#define CDP_QUALIFIERS \
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(arm_cdp_qualifiers)
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/* void (unsigned immediate, unsigned immediate, const void *). */
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static enum arm_type_qualifiers
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arm_ldc_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_void, qualifier_unsigned_immediate,
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qualifier_unsigned_immediate, qualifier_const_pointer };
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#define LDC_QUALIFIERS \
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(arm_ldc_qualifiers)
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/* void (unsigned immediate, unsigned immediate, void *). */
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static enum arm_type_qualifiers
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arm_stc_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_void, qualifier_unsigned_immediate,
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qualifier_unsigned_immediate, qualifier_pointer };
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#define STC_QUALIFIERS \
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(arm_stc_qualifiers)
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/* The first argument (return type) of a store should be void type,
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which we represent with qualifier_void. Their first operand will be
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a DImode pointer to the location to store to, so we must use
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@ -177,6 +177,7 @@ extern void arm_split_compare_and_swap (rtx op[]);
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extern void arm_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
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extern rtx arm_load_tp (rtx);
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extern bool arm_coproc_builtin_available (enum unspecv);
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extern bool arm_coproc_ldc_stc_legitimate_address (rtx);
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#if defined TREE_CODE
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extern void arm_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree);
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@ -30904,10 +30904,18 @@ arm_coproc_builtin_available (enum unspecv builtin)
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switch (builtin)
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{
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case VUNSPEC_CDP:
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case VUNSPEC_LDC:
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case VUNSPEC_LDCL:
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case VUNSPEC_STC:
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case VUNSPEC_STCL:
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if (arm_arch4)
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return true;
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break;
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case VUNSPEC_CDP2:
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case VUNSPEC_LDC2:
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case VUNSPEC_LDC2L:
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case VUNSPEC_STC2:
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case VUNSPEC_STC2L:
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/* Only present in ARMv5*, ARMv6 (but not ARMv6-M), ARMv7* and
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ARMv8-{A,M}. */
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if (arm_arch5)
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@ -30918,4 +30926,55 @@ arm_coproc_builtin_available (enum unspecv builtin)
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}
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return false;
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}
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/* This function returns true if OP is a valid memory operand for the ldc and
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stc coprocessor instructions and false otherwise. */
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bool
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arm_coproc_ldc_stc_legitimate_address (rtx op)
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{
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HOST_WIDE_INT range;
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/* Has to be a memory operand. */
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if (!MEM_P (op))
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return false;
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op = XEXP (op, 0);
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/* We accept registers. */
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if (REG_P (op))
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return true;
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switch GET_CODE (op)
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{
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case PLUS:
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{
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/* Or registers with an offset. */
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if (!REG_P (XEXP (op, 0)))
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return false;
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op = XEXP (op, 1);
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/* The offset must be an immediate though. */
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if (!CONST_INT_P (op))
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return false;
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range = INTVAL (op);
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/* Within the range of [-1020,1020]. */
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if (!IN_RANGE (range, -1020, 1020))
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return false;
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/* And a multiple of 4. */
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return (range % 4) == 0;
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}
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case PRE_INC:
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case POST_INC:
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case PRE_DEC:
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case POST_DEC:
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return REG_P (XEXP (op, 0));
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default:
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gcc_unreachable ();
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}
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return false;
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}
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#include "gt-arm.h"
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@ -11939,6 +11939,44 @@
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[(set_attr "length" "4")
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(set_attr "type" "coproc")])
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(define_insn "*ldc"
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[(unspec_volatile [(match_operand:SI 0 "immediate_operand" "n")
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(match_operand:SI 1 "immediate_operand" "n")
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(match_operand:SI 2 "memory_operand" "Uz")] LDCI)]
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"arm_coproc_builtin_available (VUNSPEC_<LDC>)"
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{
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arm_const_bounds (operands[0], 0, 16);
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arm_const_bounds (operands[1], 0, (1 << 5));
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return "<ldc>\\tp%c0, CR%c1, %2";
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}
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[(set_attr "length" "4")
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(set_attr "type" "coproc")])
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(define_insn "*stc"
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[(unspec_volatile [(match_operand:SI 0 "immediate_operand" "n")
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(match_operand:SI 1 "immediate_operand" "n")
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(match_operand:SI 2 "memory_operand" "=Uz")] STCI)]
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"arm_coproc_builtin_available (VUNSPEC_<STC>)"
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{
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arm_const_bounds (operands[0], 0, 16);
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arm_const_bounds (operands[1], 0, (1 << 5));
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return "<stc>\\tp%c0, CR%c1, %2";
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}
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[(set_attr "length" "4")
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(set_attr "type" "coproc")])
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(define_expand "<ldc>"
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[(unspec_volatile [(match_operand:SI 0 "immediate_operand")
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(match_operand:SI 1 "immediate_operand")
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(mem:SI (match_operand:SI 2 "s_register_operand"))] LDCI)]
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"arm_coproc_builtin_available (VUNSPEC_<LDC>)")
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(define_expand "<stc>"
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[(unspec_volatile [(match_operand:SI 0 "immediate_operand")
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(match_operand:SI 1 "immediate_operand")
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(mem:SI (match_operand:SI 2 "s_register_operand"))] STCI)]
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"arm_coproc_builtin_available (VUNSPEC_<STC>)")
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;; Vector bits common to IWMMXT and Neon
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(include "vec-common.md")
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;; Load the Intel Wireless Multimedia Extension patterns
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@ -41,6 +41,33 @@ __arm_cdp (const unsigned int __coproc, const unsigned int __opc1,
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return __builtin_arm_cdp (__coproc, __opc1, __CRd, __CRn, __CRm, __opc2);
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}
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__extension__ static __inline void __attribute__ ((__always_inline__))
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__arm_ldc (const unsigned int __coproc, const unsigned int __CRd,
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const void * __p)
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{
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return __builtin_arm_ldc (__coproc, __CRd, __p);
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}
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__extension__ static __inline void __attribute__ ((__always_inline__))
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__arm_ldcl (const unsigned int __coproc, const unsigned int __CRd,
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const void * __p)
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{
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return __builtin_arm_ldcl (__coproc, __CRd, __p);
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}
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__extension__ static __inline void __attribute__ ((__always_inline__))
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__arm_stc (const unsigned int __coproc, const unsigned int __CRd,
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void * __p)
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{
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return __builtin_arm_stc (__coproc, __CRd, __p);
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}
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__extension__ static __inline void __attribute__ ((__always_inline__))
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__arm_stcl (const unsigned int __coproc, const unsigned int __CRd,
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void * __p)
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{
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return __builtin_arm_stcl (__coproc, __CRd, __p);
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}
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#if __ARM_ARCH >= 5
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__extension__ static __inline void __attribute__ ((__always_inline__))
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__arm_cdp2 (const unsigned int __coproc, const unsigned int __opc1,
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@ -49,6 +76,34 @@ __arm_cdp2 (const unsigned int __coproc, const unsigned int __opc1,
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{
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return __builtin_arm_cdp2 (__coproc, __opc1, __CRd, __CRn, __CRm, __opc2);
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}
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__extension__ static __inline void __attribute__ ((__always_inline__))
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__arm_ldc2 (const unsigned int __coproc, const unsigned int __CRd,
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const void * __p)
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{
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return __builtin_arm_ldc2 (__coproc, __CRd, __p);
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}
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__extension__ static __inline void __attribute__ ((__always_inline__))
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__arm_ldc2l (const unsigned int __coproc, const unsigned int __CRd,
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const void * __p)
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{
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return __builtin_arm_ldc2l (__coproc, __CRd, __p);
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}
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__extension__ static __inline void __attribute__ ((__always_inline__))
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__arm_stc2 (const unsigned int __coproc, const unsigned int __CRd,
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void * __p)
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{
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return __builtin_arm_stc2 (__coproc, __CRd, __p);
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}
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__extension__ static __inline void __attribute__ ((__always_inline__))
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__arm_stc2l (const unsigned int __coproc, const unsigned int __CRd,
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void * __p)
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{
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return __builtin_arm_stc2l (__coproc, __CRd, __p);
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}
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#endif /* __ARM_ARCH >= 5. */
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#endif /* (!__thumb__ || __thumb2__) && __ARM_ARCH >= 4. */
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@ -26,3 +26,11 @@ VAR1 (UBINOP, crc32ch, si)
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VAR1 (UBINOP, crc32cw, si)
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VAR1 (CDP, cdp, void)
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VAR1 (CDP, cdp2, void)
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VAR1 (LDC, ldc, void)
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VAR1 (LDC, ldc2, void)
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VAR1 (LDC, ldcl, void)
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VAR1 (LDC, ldc2l, void)
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VAR1 (STC, stc, void)
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VAR1 (STC, stc2, void)
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VAR1 (STC, stcl, void)
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VAR1 (STC, stc2l, void)
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@ -447,6 +447,12 @@
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(match_code "symbol_ref")
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)
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(define_memory_constraint "Uz"
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"@internal
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A memory access that is accessible as an LDC/STC operand"
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(and (match_code "mem")
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(match_test "arm_coproc_ldc_stc_legitimate_address (op)")))
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;; We used to have constraint letters for S and R in ARM state, but
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;; all uses of these now appear to have been removed.
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@ -948,3 +948,19 @@
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(define_int_iterator CDPI [VUNSPEC_CDP VUNSPEC_CDP2])
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(define_int_attr cdp [(VUNSPEC_CDP "cdp") (VUNSPEC_CDP2 "cdp2")])
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(define_int_attr CDP [(VUNSPEC_CDP "CDP") (VUNSPEC_CDP2 "CDP2")])
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;; An iterator for the LDC coprocessor instruction
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(define_int_iterator LDCI [VUNSPEC_LDC VUNSPEC_LDC2
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VUNSPEC_LDCL VUNSPEC_LDC2L])
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(define_int_attr ldc [(VUNSPEC_LDC "ldc") (VUNSPEC_LDC2 "ldc2")
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(VUNSPEC_LDCL "ldcl") (VUNSPEC_LDC2L "ldc2l")])
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(define_int_attr LDC [(VUNSPEC_LDC "LDC") (VUNSPEC_LDC2 "LDC2")
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(VUNSPEC_LDCL "LDCL") (VUNSPEC_LDC2L "LDC2L")])
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;; An iterator for the STC coprocessor instructions
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(define_int_iterator STCI [VUNSPEC_STC VUNSPEC_STC2
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VUNSPEC_STCL VUNSPEC_STC2L])
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(define_int_attr stc [(VUNSPEC_STC "stc") (VUNSPEC_STC2 "stc2")
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(VUNSPEC_STCL "stcl") (VUNSPEC_STC2L "stc2l")])
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(define_int_attr STC [(VUNSPEC_STC "STC") (VUNSPEC_STC2 "STC2")
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(VUNSPEC_STCL "STCL") (VUNSPEC_STC2L "STC2L")])
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@ -152,6 +152,14 @@
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VUNSPEC_PROBE_STACK_RANGE ; Represent stack range probing.
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VUNSPEC_CDP ; Represent the coprocessor cdp instruction.
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VUNSPEC_CDP2 ; Represent the coprocessor cdp2 instruction.
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VUNSPEC_LDC ; Represent the coprocessor ldc instruction.
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VUNSPEC_LDC2 ; Represent the coprocessor ldc2 instruction.
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VUNSPEC_LDCL ; Represent the coprocessor ldcl instruction.
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VUNSPEC_LDC2L ; Represent the coprocessor ldc2l instruction.
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VUNSPEC_STC ; Represent the coprocessor stc instruction.
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VUNSPEC_STC2 ; Represent the coprocessor stc2 instruction.
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VUNSPEC_STCL ; Represent the coprocessor stcl instruction.
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VUNSPEC_STC2L ; Represent the coprocessor stc2l instruction.
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])
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;; Enumerators for NEON unspecs.
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@ -1,3 +1,14 @@
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2017-01-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* gcc.target/arm/acle/ldc: New.
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* gcc.target/arm/acle/ldc2: New.
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* gcc.target/arm/acle/ldcl: New.
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* gcc.target/arm/acle/ldc2l: New.
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* gcc.target/arm/acle/stc: New.
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* gcc.target/arm/acle/stc2: New.
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* gcc.target/arm/acle/stcl: New.
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* gcc.target/arm/acle/stc2l: New.
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2017-01-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* gcc.target/arm/acle/acle.exp: Run tests for different options
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@ -0,0 +1,18 @@
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/* Test the ldc ACLE intrinsic. */
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/* { dg-do assemble } */
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/* { dg-options "-save-temps" } */
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/* { dg-require-effective-target arm_coproc1_ok } */
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#include "arm_acle.h"
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extern void * p;
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void test_ldc (void)
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{
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__arm_ldc (10, 1, p + 4);
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__arm_ldc (11, 1, p + 1024);
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}
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/* { dg-final { scan-assembler "ldc\tp10, CR1, \[r\[0-9\]+" } } */
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/* { dg-final { scan-assembler "ldc\tp11, CR1, \[r\[0-9\]+\]\n" } } */
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/* Test the ldc2 ACLE intrinsic. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-options "-save-temps" } */
|
||||
/* { dg-require-effective-target arm_coproc2_ok } */
|
||||
|
||||
#include "arm_acle.h"
|
||||
|
||||
extern void * p;
|
||||
|
||||
void test_ldc2 (void)
|
||||
{
|
||||
__arm_ldc2 (10, 1, p - 120);
|
||||
__arm_ldc2 (11, 1, p - 122);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "ldc2\tp10, CR1, \[r\[0-9\]+" } } */
|
||||
/* { dg-final { scan-assembler "ldc2\tp11, CR1, \[r\[0-9\]+\]\n" } } */
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/* Test the ldc2l ACLE intrinsic. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-options "-save-temps" } */
|
||||
/* { dg-require-effective-target arm_coproc2_ok } */
|
||||
|
||||
#include "arm_acle.h"
|
||||
|
||||
extern void * p;
|
||||
|
||||
void test_ldc2l (void)
|
||||
{
|
||||
__arm_ldc2l (10, 1, p - 120);
|
||||
__arm_ldc2l (11, 1, p - 122);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "ldc2l\tp10, CR1, \[r\[0-9\]+" } } */
|
||||
/* { dg-final { scan-assembler "ldc2l\tp11, CR1, \[r\[0-9\]+\]\n" } } */
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/* Test the ldcl ACLE intrinsic. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-options "-save-temps" } */
|
||||
/* { dg-require-effective-target arm_coproc1_ok } */
|
||||
|
||||
#include "arm_acle.h"
|
||||
|
||||
extern void * p;
|
||||
|
||||
void test_ldcl (void)
|
||||
{
|
||||
__arm_ldcl (10, 1, p + 4);
|
||||
__arm_ldcl (11, 1, p + 1024);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "ldcl\tp10, CR1, \[r\[0-9\]+" } } */
|
||||
/* { dg-final { scan-assembler "ldcl\tp11, CR1, \[r\[0-9\]+\]\n" } } */
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/* Test the stc ACLE intrinsic. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-options "-save-temps" } */
|
||||
/* { dg-require-effective-target arm_coproc1_ok } */
|
||||
|
||||
#include "arm_acle.h"
|
||||
|
||||
extern void * p;
|
||||
|
||||
void test_stc (void)
|
||||
{
|
||||
__arm_stc (10, 1, p + 4);
|
||||
__arm_stc (11, 1, p + 1024);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "stc\tp10, CR1, \[r\[0-9\]+" } } */
|
||||
/* { dg-final { scan-assembler "stc\tp11, CR1, \[r\[0-9\]+\]\n" } } */
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/* Test the stc2 ACLE intrinsic. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-options "-save-temps" } */
|
||||
/* { dg-require-effective-target arm_coproc2_ok } */
|
||||
|
||||
#include "arm_acle.h"
|
||||
|
||||
extern void * p;
|
||||
|
||||
void test_stc2 (void)
|
||||
{
|
||||
__arm_stc2 (10, 1, p - 120);
|
||||
__arm_stc2 (11, 1, p - 122);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "stc2\tp10, CR1, \[r\[0-9\]+" } } */
|
||||
/* { dg-final { scan-assembler "stc2\tp11, CR1, \[r\[0-9\]+\]\n" } } */
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/* Test the stc2l ACLE intrinsic. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-options "-save-temps" } */
|
||||
/* { dg-require-effective-target arm_coproc2_ok } */
|
||||
|
||||
#include "arm_acle.h"
|
||||
|
||||
extern void * p;
|
||||
|
||||
void test_stc2l (void)
|
||||
{
|
||||
__arm_stc2l (10, 1, p - 120);
|
||||
__arm_stc2l (11, 1, p - 122);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "stc2l\tp10, CR1, \[r\[0-9\]+" } } */
|
||||
/* { dg-final { scan-assembler "stc2l\tp11, CR1, \[r\[0-9\]+\]\n" } } */
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/* Test the stcl ACLE intrinsic. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-options "-save-temps" } */
|
||||
/* { dg-require-effective-target arm_coproc1_ok } */
|
||||
|
||||
#include "arm_acle.h"
|
||||
|
||||
extern void * p;
|
||||
|
||||
void test_stcl (void)
|
||||
{
|
||||
__arm_stcl (14, 10, p + 4);
|
||||
__arm_stcl (10, 10, p + 1024);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "stcl\tp14, CR10, \[r\[0-9\]+" } } */
|
||||
/* { dg-final { scan-assembler "stcl\tp10, CR10, \[r\[0-9\]+\]\n" } } */
|
||||
Loading…
Reference in New Issue