[AArch64] Add more SVE FMLA and FMAD /z alternatives
This patch makes the floating-point conditional FMA patterns provide the same /z alternatives as the integer patterns added by a previous patch. We can handle cases in which individual inputs are allocated to the same register as the output, so we don't need to force all registers to be different. 2019-08-15 Richard Sandiford <richard.sandiford@arm.com> Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org> gcc/ * config/aarch64/aarch64-sve.md (*cond_<SVE_COND_FP_TERNARY:optab><SVE_F:mode>_any): Add /z alternatives in which one of the inputs is in the same register as the output. gcc/testsuite/ * gcc.target/aarch64/sve/cond_mla_5.c: Allow FMAD as well as FMLA and FMSB as well as FMLS. Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org> From-SVN: r274516
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@ -1,3 +1,11 @@
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2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
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Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
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* config/aarch64/aarch64-sve.md
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(*cond_<SVE_COND_FP_TERNARY:optab><SVE_F:mode>_any): Add /z
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alternatives in which one of the inputs is in the same register
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as the output.
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2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64-sve.md (*vec_extract<mode><Vel>_ext)
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@ -3844,17 +3844,17 @@
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;; Predicated floating-point ternary operations, merging with an
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;; independent value.
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(define_insn_and_rewrite "*cond_<optab><mode>_any"
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[(set (match_operand:SVE_F 0 "register_operand" "=&w, &w, ?&w")
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[(set (match_operand:SVE_F 0 "register_operand" "=&w, &w, &w, &w, &w, ?&w")
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(unspec:SVE_F
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl")
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl, Upl, Upl, Upl")
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(unspec:SVE_F
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[(match_operand 6)
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(match_operand:SI 7 "aarch64_sve_gp_strictness")
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(match_operand:SVE_F 2 "register_operand" "w, w, w")
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(match_operand:SVE_F 3 "register_operand" "w, w, w")
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(match_operand:SVE_F 4 "register_operand" "w, w, w")]
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(match_operand:SVE_F 2 "register_operand" "w, w, 0, w, w, w")
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(match_operand:SVE_F 3 "register_operand" "w, w, w, 0, w, w")
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(match_operand:SVE_F 4 "register_operand" "w, 0, w, w, w, w")]
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SVE_COND_FP_TERNARY)
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(match_operand:SVE_F 5 "aarch64_simd_reg_or_zero" "Dz, 0, w")]
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(match_operand:SVE_F 5 "aarch64_simd_reg_or_zero" "Dz, Dz, Dz, Dz, 0, w")]
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UNSPEC_SEL))]
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"TARGET_SVE
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&& !rtx_equal_p (operands[2], operands[5])
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@ -3863,6 +3863,9 @@
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&& aarch64_sve_pred_dominates_p (&operands[6], operands[1])"
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"@
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movprfx\t%0.<Vetype>, %1/z, %4.<Vetype>\;<sve_fmla_op>\t%0.<Vetype>, %1/m, %2.<Vetype>, %3.<Vetype>
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movprfx\t%0.<Vetype>, %1/z, %0.<Vetype>\;<sve_fmla_op>\t%0.<Vetype>, %1/m, %2.<Vetype>, %3.<Vetype>
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movprfx\t%0.<Vetype>, %1/z, %0.<Vetype>\;<sve_fmad_op>\t%0.<Vetype>, %1/m, %3.<Vetype>, %4.<Vetype>
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movprfx\t%0.<Vetype>, %1/z, %0.<Vetype>\;<sve_fmad_op>\t%0.<Vetype>, %1/m, %2.<Vetype>, %4.<Vetype>
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movprfx\t%0.<Vetype>, %1/m, %4.<Vetype>\;<sve_fmla_op>\t%0.<Vetype>, %1/m, %2.<Vetype>, %3.<Vetype>
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#"
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"&& 1"
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@ -1,3 +1,9 @@
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2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
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Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
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* gcc.target/aarch64/sve/cond_mla_5.c: Allow FMAD as well as FMLA
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and FMSB as well as FMLS.
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2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
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* gcc.target/aarch64/sve/ext_2.c: Expect a MOVPRFX.
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@ -39,13 +39,13 @@ TEST_ALL (DEF_LOOP)
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/* { dg-final { scan-assembler-times {\t(?:mls|msb)\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\t(?:mls|msb)\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmla\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmla\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmla\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\t(?:fmla|fmad)\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\t(?:fmla|fmad)\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\t(?:fmla|fmad)\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmls\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmls\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmls\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\t(?:fmls|fmsb)\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\t(?:fmls|fmsb)\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\t(?:fmls|fmsb)\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.b, p[0-7]/z,} 2 } } */
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/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z,} 4 } } */
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