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[testsuite/ARM] Fix coprocessor intrinsic test failures on ARMv8-A

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Coprocessor intrinsic tests in gcc.target/arm/acle test whether
__ARM_FEATURE_COPROC has the right bit defined before calling the
intrinsic. This allows to test both the correct setting of that macro
and the availability and correct working of the intrinsic. However the
__ARM_FEATURE_COPROC macro is no longer defined for ARMv8-A since
r249399.

This patch changes the testcases to skip that test for ARMv8-A and
ARMv8-R targets.  It also fixes some irregularity in the coprocessor
effective targets:
- add ldcl and stcl to the list of instructions listed as guarded by
  arm_coproc1_ok
- enable tests guarded by arm_coproc2_ok, arm_coproc3_ok and
  arm_coproc4_ok for Thumb-2 capable targets but disable for Thumb-1
  targets.

2017-09-13  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/testsuite/
    * gcc.target/arm/acle/cdp.c: Skip __ARM_FEATURE_COPROC check for
    ARMv8-A and ARMv8-R.
    * gcc.target/arm/acle/cdp2.c: Likewise.
    * gcc.target/arm/acle/ldc.c: Likewise.
    * gcc.target/arm/acle/ldc2.c: Likewise.
    * gcc.target/arm/acle/ldc2l.c: Likewise.
    * gcc.target/arm/acle/ldcl.c: Likewise.
    * gcc.target/arm/acle/mcr.c: Likewise.
    * gcc.target/arm/acle/mcr2.c: Likewise.
    * gcc.target/arm/acle/mcrr.c: Likewise.
    * gcc.target/arm/acle/mcrr2.c: Likewise.
    * gcc.target/arm/acle/mrc.c: Likewise.
    * gcc.target/arm/acle/mrc2.c: Likewise.
    * gcc.target/arm/acle/mrrc.c: Likewise.
    * gcc.target/arm/acle/mrrc2.c: Likewise.
    * gcc.target/arm/acle/stc.c: Likewise.
    * gcc.target/arm/acle/stc2.c: Likewise.
    * gcc.target/arm/acle/stc2l.c: Likewise.
    * gcc.target/arm/acle/stcl.c: Likewise.
    * lib/target-supports.exp:
    (check_effective_target_arm_coproc1_ok_nocache): Mention ldcl
    and stcl in the comment.
    (check_effective_target_arm_coproc2_ok_nocache): Allow Thumb-2 targets
    and disable Thumb-1 targets.
    (check_effective_target_arm_coproc3_ok_nocache): Likewise.
    (check_effective_target_arm_coproc4_ok_nocache): Likewise.

Acked-by: Kyrill Tkachov <kyrylo.tkachov@foss.arm.com>

From-SVN: r252074
This commit is contained in:
Thomas Preud'homme 2017-09-13 10:27:00 +00:00 committed by Thomas Preud'homme
parent c29730ec17
commit 4395a47389
20 changed files with 71 additions and 23 deletions
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29
gcc/testsuite/ChangeLog
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@ -1,3 +1,32 @@
2017-09-13 Thomas Preud'homme <thomas.preudhomme@arm.com>
* gcc.target/arm/acle/cdp.c: Skip __ARM_FEATURE_COPROC check for
ARMv8-A and ARMv8-R.
* gcc.target/arm/acle/cdp2.c: Likewise.
* gcc.target/arm/acle/ldc.c: Likewise.
* gcc.target/arm/acle/ldc2.c: Likewise.
* gcc.target/arm/acle/ldc2l.c: Likewise.
* gcc.target/arm/acle/ldcl.c: Likewise.
* gcc.target/arm/acle/mcr.c: Likewise.
* gcc.target/arm/acle/mcr2.c: Likewise.
* gcc.target/arm/acle/mcrr.c: Likewise.
* gcc.target/arm/acle/mcrr2.c: Likewise.
* gcc.target/arm/acle/mrc.c: Likewise.
* gcc.target/arm/acle/mrc2.c: Likewise.
* gcc.target/arm/acle/mrrc.c: Likewise.
* gcc.target/arm/acle/mrrc2.c: Likewise.
* gcc.target/arm/acle/stc.c: Likewise.
* gcc.target/arm/acle/stc2.c: Likewise.
* gcc.target/arm/acle/stc2l.c: Likewise.
* gcc.target/arm/acle/stcl.c: Likewise.
* lib/target-supports.exp:
(check_effective_target_arm_coproc1_ok_nocache): Mention ldcl
and stcl in the comment.
(check_effective_target_arm_coproc2_ok_nocache): Allow Thumb-2 targets
and disable Thumb-1 targets.
(check_effective_target_arm_coproc3_ok_nocache): Likewise.
(check_effective_target_arm_coproc4_ok_nocache): Likewise.
2017-09-13 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/47226

3
gcc/testsuite/gcc.target/arm/acle/cdp.c
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@ -5,7 +5,8 @@
/* { dg-require-effective-target arm_coproc1_ok } */
#include "arm_acle.h"
#if (__ARM_FEATURE_COPROC & 0x1) == 0
#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
&& (__ARM_FEATURE_COPROC & 0x1) == 0
#error "__ARM_FEATURE_COPROC does not have correct feature bits set"
#endif

3
gcc/testsuite/gcc.target/arm/acle/cdp2.c
View File

@ -5,7 +5,8 @@
/* { dg-require-effective-target arm_coproc2_ok } */
#include "arm_acle.h"
#if (__ARM_FEATURE_COPROC & 0x2) == 0
#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
&& (__ARM_FEATURE_COPROC & 0x2) == 0
#error "__ARM_FEATURE_COPROC does not have correct feature bits set"
#endif

3
gcc/testsuite/gcc.target/arm/acle/ldc.c
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@ -5,7 +5,8 @@
/* { dg-require-effective-target arm_coproc1_ok } */
#include "arm_acle.h"
#if (__ARM_FEATURE_COPROC & 0x1) == 0
#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
&& (__ARM_FEATURE_COPROC & 0x1) == 0
#error "__ARM_FEATURE_COPROC does not have correct feature bits set"
#endif

3
gcc/testsuite/gcc.target/arm/acle/ldc2.c
View File

@ -5,7 +5,8 @@
/* { dg-require-effective-target arm_coproc2_ok } */
#include "arm_acle.h"
#if (__ARM_FEATURE_COPROC & 0x2) == 0
#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
&& (__ARM_FEATURE_COPROC & 0x2) == 0
#error "__ARM_FEATURE_COPROC does not have correct feature bits set"
#endif

3
gcc/testsuite/gcc.target/arm/acle/ldc2l.c
View File

@ -5,7 +5,8 @@
/* { dg-require-effective-target arm_coproc2_ok } */
#include "arm_acle.h"
#if (__ARM_FEATURE_COPROC & 0x2) == 0
#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
&& (__ARM_FEATURE_COPROC & 0x2) == 0
#error "__ARM_FEATURE_COPROC does not have correct feature bits set"
#endif

3
gcc/testsuite/gcc.target/arm/acle/ldcl.c
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@ -5,7 +5,8 @@
/* { dg-require-effective-target arm_coproc1_ok } */
#include "arm_acle.h"
#if (__ARM_FEATURE_COPROC & 0x1) == 0
#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
&& (__ARM_FEATURE_COPROC & 0x1) == 0
#error "__ARM_FEATURE_COPROC does not have correct feature bits set"
#endif

3
gcc/testsuite/gcc.target/arm/acle/mcr.c
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@ -5,7 +5,8 @@
/* { dg-require-effective-target arm_coproc1_ok } */
#include "arm_acle.h"
#if (__ARM_FEATURE_COPROC & 0x1) == 0
#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
&& (__ARM_FEATURE_COPROC & 0x1) == 0
#error "__ARM_FEATURE_COPROC does not have correct feature bits set"
#endif

3
gcc/testsuite/gcc.target/arm/acle/mcr2.c
View File

@ -5,7 +5,8 @@
/* { dg-require-effective-target arm_coproc2_ok } */
#include "arm_acle.h"
#if (__ARM_FEATURE_COPROC & 0x2) == 0
#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
&& (__ARM_FEATURE_COPROC & 0x2) == 0
#error "__ARM_FEATURE_COPROC does not have correct feature bits set"
#endif

3
gcc/testsuite/gcc.target/arm/acle/mcrr.c
View File

@ -5,7 +5,8 @@
/* { dg-require-effective-target arm_coproc3_ok } */
#include "arm_acle.h"
#if (__ARM_FEATURE_COPROC & 0x4) == 0
#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
&& (__ARM_FEATURE_COPROC & 0x4) == 0
#error "__ARM_FEATURE_COPROC does not have correct feature bits set"
#endif

3
gcc/testsuite/gcc.target/arm/acle/mcrr2.c
View File

@ -5,7 +5,8 @@
/* { dg-require-effective-target arm_coproc4_ok } */
#include "arm_acle.h"
#if (__ARM_FEATURE_COPROC & 0x8) == 0
#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
&& (__ARM_FEATURE_COPROC & 0x8) == 0
#error "__ARM_FEATURE_COPROC does not have correct feature bits set"
#endif

3
gcc/testsuite/gcc.target/arm/acle/mrc.c
View File

@ -5,7 +5,8 @@
/* { dg-require-effective-target arm_coproc1_ok } */
#include "arm_acle.h"
#if (__ARM_FEATURE_COPROC & 0x1) == 0
#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
&& (__ARM_FEATURE_COPROC & 0x1) == 0
#error "__ARM_FEATURE_COPROC does not have correct feature bits set"
#endif

3
gcc/testsuite/gcc.target/arm/acle/mrc2.c
View File

@ -5,7 +5,8 @@
/* { dg-require-effective-target arm_coproc2_ok } */
#include "arm_acle.h"
#if (__ARM_FEATURE_COPROC & 0x2) == 0
#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
&& (__ARM_FEATURE_COPROC & 0x2) == 0
#error "__ARM_FEATURE_COPROC does not have correct feature bits set"
#endif

3
gcc/testsuite/gcc.target/arm/acle/mrrc.c
View File

@ -5,7 +5,8 @@
/* { dg-require-effective-target arm_coproc3_ok } */
#include "arm_acle.h"
#if (__ARM_FEATURE_COPROC & 0x4) == 0
#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
&& (__ARM_FEATURE_COPROC & 0x4) == 0
#error "__ARM_FEATURE_COPROC does not have correct feature bits set"
#endif

3
gcc/testsuite/gcc.target/arm/acle/mrrc2.c
View File

@ -5,7 +5,8 @@
/* { dg-require-effective-target arm_coproc4_ok } */
#include "arm_acle.h"
#if (__ARM_FEATURE_COPROC & 0x8) == 0
#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
&& (__ARM_FEATURE_COPROC & 0x8) == 0
#error "__ARM_FEATURE_COPROC does not have correct feature bits set"
#endif

3
gcc/testsuite/gcc.target/arm/acle/stc.c
View File

@ -5,7 +5,8 @@
/* { dg-require-effective-target arm_coproc1_ok } */
#include "arm_acle.h"
#if (__ARM_FEATURE_COPROC & 0x1) == 0
#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
&& (__ARM_FEATURE_COPROC & 0x1) == 0
#error "__ARM_FEATURE_COPROC does not have correct feature bits set"
#endif

3
gcc/testsuite/gcc.target/arm/acle/stc2.c
View File

@ -5,7 +5,8 @@
/* { dg-require-effective-target arm_coproc2_ok } */
#include "arm_acle.h"
#if (__ARM_FEATURE_COPROC & 0x2) == 0
#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
&& (__ARM_FEATURE_COPROC & 0x2) == 0
#error "__ARM_FEATURE_COPROC does not have correct feature bits set"
#endif

3
gcc/testsuite/gcc.target/arm/acle/stc2l.c
View File

@ -5,7 +5,8 @@
/* { dg-require-effective-target arm_coproc2_ok } */
#include "arm_acle.h"
#if (__ARM_FEATURE_COPROC & 0x2) == 0
#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
&& (__ARM_FEATURE_COPROC & 0x2) == 0
#error "__ARM_FEATURE_COPROC does not have correct feature bits set"
#endif

3
gcc/testsuite/gcc.target/arm/acle/stcl.c
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@ -5,7 +5,8 @@
/* { dg-require-effective-target arm_coproc1_ok } */
#include "arm_acle.h"
#if (__ARM_FEATURE_COPROC & 0x1) == 0
#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \
&& (__ARM_FEATURE_COPROC & 0x1) == 0
#error "__ARM_FEATURE_COPROC does not have correct feature bits set"
#endif

11
gcc/testsuite/lib/target-supports.exp
View File

@ -8504,8 +8504,8 @@ proc check_effective_target_rdrand { } {
} "-mrdrnd" ]
}
# Return 1 if the target supports coprocessor instructions: cdp, ldc, stc, mcr and
# mrc.
# Return 1 if the target supports coprocessor instructions: cdp, ldc, ldcl,
# stc, stcl, mcr and mrc.
proc check_effective_target_arm_coproc1_ok_nocache { } {
if { ![istarget arm*-*-*] } {
return 0
@ -8530,7 +8530,7 @@ proc check_effective_target_arm_coproc2_ok_nocache { } {
return 0
}
return [check_no_compiler_messages_nocache arm_coproc2_ok assembly {
#if __ARM_ARCH < 5
#if (__thumb__ && !__thumb2__) || __ARM_ARCH < 5
#error FOO
#endif
}]
@ -8549,7 +8549,8 @@ proc check_effective_target_arm_coproc3_ok_nocache { } {
return 0
}
return [check_no_compiler_messages_nocache arm_coproc3_ok assembly {
#if __ARM_ARCH < 6 && !defined (__ARM_ARCH_5TE__)
#if (__thumb__ && !__thumb2__) \
|| (__ARM_ARCH < 6 && !defined (__ARM_ARCH_5TE__))
#error FOO
#endif
}]
@ -8568,7 +8569,7 @@ proc check_effective_target_arm_coproc4_ok_nocache { } {
return 0
}
return [check_no_compiler_messages_nocache arm_coproc4_ok assembly {
#if __ARM_ARCH < 6
#if (__thumb__ && !__thumb2__) || __ARM_ARCH < 6
#error FOO
#endif
}]