arm.md (attribute "insn"): Delete values "mrs", "msr", "xtab" and "sat".
* config/arm/arm.md (attribute "insn"): Delete values "mrs", "msr", "xtab" and "sat". Move value "clz" from here to ... (attriubte "type"): ... here. (satsi_<SAT:code>): Delete "insn" attribute. (satsi_<SAT:code>_shift): Likewise. (arm_zero_extendqisi2addsi): Likewise. (arm_extendqisi2addsi): Likewise. (clzsi2): Update for attribute changes. (rbitsi2): Likewise. * config/arm/arm-fixed.md (arm_ssatsihi_shift): Delete "insn" attribute. (arm_usatsihi): Likewise. * config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute change. From-SVN: r201025
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@ -1,3 +1,18 @@
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2013-07-18 Sofiane Naci <sofiane.naci@arm.com>
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* config/arm/arm.md (attribute "insn"): Delete values "mrs", "msr",
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"xtab" and "sat". Move value "clz" from here to ...
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(attriubte "type"): ... here.
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(satsi_<SAT:code>): Delete "insn" attribute.
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(satsi_<SAT:code>_shift): Likewise.
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(arm_zero_extendqisi2addsi): Likewise.
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(arm_extendqisi2addsi): Likewise.
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(clzsi2): Update for attribute changes.
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(rbitsi2): Likewise.
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* config/arm/arm-fixed.md (arm_ssatsihi_shift): Delete "insn" attribute.
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(arm_usatsihi): Likewise.
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* config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute change.
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2013-07-18 Sofiane Naci <sofiane.naci@arm.com>
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* config/arm/arm.md (attribute "type"): Rename "simple_alu_imm" to
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@ -383,7 +383,6 @@
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"ssat%?\\t%0, #16, %2%S1"
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[(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")
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(set_attr "insn" "sat")
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(set_attr "shift" "1")
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(set_attr "type" "arlo_shift")])
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@ -393,5 +392,5 @@
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"TARGET_INT_SIMD"
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"usat%?\\t%0, #16, %1"
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[(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")
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(set_attr "insn" "sat")])
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(set_attr "predicable_short_it" "no")]
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)
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@ -250,7 +250,7 @@
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;; scheduling information.
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(define_attr "insn"
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"mov,mvn,clz,mrs,msr,xtab,sat,other"
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"mov,mvn,other"
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(const_string "other"))
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; TYPE attribute is used to classify instructions for use in scheduling.
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@ -271,6 +271,7 @@
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; block blockage insn, this blocks all functional units.
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; branch branch.
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; call subroutine call.
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; clz count leading zeros (CLZ).
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; extend extend instruction (SXTB, SXTH, UXTB, UXTH).
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; f_2_r transfer from float to core (no memory needed).
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; f_cvt conversion between float and integral.
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@ -412,7 +413,7 @@
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block,\
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branch,\
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call,\
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complex,\
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clz,\
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extend,\
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f_2_r,\
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f_cvt,\
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@ -4036,8 +4037,8 @@
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else
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return "usat%?\t%0, %1, %3";
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}
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[(set_attr "predicable" "yes")
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(set_attr "insn" "sat")])
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[(set_attr "predicable" "yes")]
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)
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(define_insn "*satsi_<SAT:code>_shift"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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@ -4062,7 +4063,6 @@
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return "usat%?\t%0, %1, %4%S3";
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}
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[(set_attr "predicable" "yes")
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(set_attr "insn" "sat")
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(set_attr "shift" "3")
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(set_attr "type" "arlo_shift")])
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@ -5669,7 +5669,6 @@
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"uxtab%?\\t%0, %2, %1"
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[(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")
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(set_attr "insn" "xtab")
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(set_attr "type" "arlo_shift")]
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)
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@ -6020,7 +6019,6 @@
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"TARGET_INT_SIMD"
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"sxtab%?\\t%0, %2, %1"
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[(set_attr "type" "arlo_shift")
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(set_attr "insn" "xtab")
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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)
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@ -12472,7 +12470,7 @@
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"TARGET_32BIT && arm_arch5"
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"clz%?\\t%0, %1"
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[(set_attr "predicable" "yes")
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(set_attr "insn" "clz")])
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(set_attr "type" "clz")])
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(define_insn "rbitsi2"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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@ -12480,7 +12478,7 @@
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"TARGET_32BIT && arm_arch_thumb2"
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"rbit%?\\t%0, %1"
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[(set_attr "predicable" "yes")
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(set_attr "insn" "clz")])
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(set_attr "type" "clz")])
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(define_expand "ctzsi2"
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[(set (match_operand:SI 0 "s_register_operand" "")
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@ -88,7 +88,7 @@
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(ior (and (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
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(eq_attr "neon_type" "none"))
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(not (eq_attr "insn" "mov,mvn")))
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(eq_attr "insn" "clz")))
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(eq_attr "type" "clz")))
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"cortex_a8_default")
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(define_insn_reservation "cortex_a8_alu_shift" 2
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