arm-cores.def (generic-armv7-a): New architecture.
2011-09-09 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/arm/arm-cores.def (generic-armv7-a): New architecture. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Regenerate. * config/arm/arm.c (arm_file_start): Output .arch directive when user passes -mcpu=generic-*. (arm_issue_rate): Add genericv7a support. * config/arm/arm.h (EXTRA_SPECS): Add asm_cpu_spec. (ASM_CPU_SPEC): New define. * config/arm/elf.h (ASM_SPEC): Use %(asm_cpu_spec). * config/arm/semi.h (ASM_SPEC): Likewise. * doc/invoke.texi (ARM Options): Document -mcpu=generic-* and -mtune=generic-*. From-SVN: r178731
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Andrew Stubbs
Andrew Stubbs
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@ -1,3 +1,18 @@
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2011-09-09 Andrew Stubbs <ams@codesourcery.com>
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* config/arm/arm-cores.def (generic-armv7-a): New architecture.
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* config/arm/arm-tables.opt: Regenerate.
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* config/arm/arm-tune.md: Regenerate.
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* config/arm/arm.c (arm_file_start): Output .arch directive when
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user passes -mcpu=generic-*.
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(arm_issue_rate): Add genericv7a support.
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* config/arm/arm.h (EXTRA_SPECS): Add asm_cpu_spec.
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(ASM_CPU_SPEC): New define.
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* config/arm/elf.h (ASM_SPEC): Use %(asm_cpu_spec).
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* config/arm/semi.h (ASM_SPEC): Likewise.
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* doc/invoke.texi (ARM Options): Document -mcpu=generic-*
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and -mtune=generic-*.
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2011-09-09 Richard Guenther <rguenther@suse.de>
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PR tree-optimization/50328
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@ -124,6 +124,7 @@ ARM_CORE("mpcorenovfp", mpcorenovfp, 6K, FL_LDSCHED, 9e)
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ARM_CORE("mpcore", mpcore, 6K, FL_LDSCHED | FL_VFPV2, 9e)
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ARM_CORE("arm1156t2-s", arm1156t2s, 6T2, FL_LDSCHED, v6t2)
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ARM_CORE("arm1156t2f-s", arm1156t2fs, 6T2, FL_LDSCHED | FL_VFPV2, v6t2)
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ARM_CORE("generic-armv7-a", genericv7a, 7A, FL_LDSCHED, cortex)
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ARM_CORE("cortex-a5", cortexa5, 7A, FL_LDSCHED, cortex_a5)
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ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, cortex)
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ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9)
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@ -135,3 +136,4 @@ ARM_CORE("cortex-m4", cortexm4, 7EM, FL_LDSCHED, cortex)
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ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, cortex)
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ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, cortex)
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ARM_CORE("cortex-m0", cortexm0, 6M, FL_LDSCHED, cortex)
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@ -231,6 +231,9 @@ Enum(processor_type) String(arm1156t2-s) Value(arm1156t2s)
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EnumValue
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Enum(processor_type) String(arm1156t2f-s) Value(arm1156t2fs)
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EnumValue
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Enum(processor_type) String(generic-armv7-a) Value(genericv7a)
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EnumValue
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Enum(processor_type) String(cortex-a5) Value(cortexa5)
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@ -1,5 +1,5 @@
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;; -*- buffer-read-only: t -*-
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;; Generated automatically by gentune.sh from arm-cores.def
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(define_attr "tune"
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"arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0"
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"arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0"
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(const (symbol_ref "((enum attr_tune) arm_tune)")))
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@ -22209,6 +22209,8 @@ arm_file_start (void)
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const char *fpu_name;
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if (arm_selected_arch)
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asm_fprintf (asm_out_file, "\t.arch %s\n", arm_selected_arch->name);
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else if (strncmp (arm_selected_cpu->name, "generic", 7) == 0)
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asm_fprintf (asm_out_file, "\t.arch %s\n", arm_selected_cpu->name + 8);
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else
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asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_selected_cpu->name);
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@ -23733,6 +23735,7 @@ arm_issue_rate (void)
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case cortexr4:
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case cortexr4f:
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case cortexr5:
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case genericv7a:
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case cortexa5:
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case cortexa8:
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case cortexa9:
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@ -189,6 +189,7 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
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Do not define this macro if it does not need to do anything. */
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#define EXTRA_SPECS \
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{ "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
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{ "asm_cpu_spec", ASM_CPU_SPEC }, \
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SUBTARGET_EXTRA_SPECS
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#ifndef SUBTARGET_EXTRA_SPECS
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@ -2223,4 +2224,8 @@ extern int making_const_table;
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instruction. */
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#define MAX_LDM_STM_OPS 4
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#define ASM_CPU_SPEC \
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" %{mcpu=generic-*:-march=%*;" \
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" :%{mcpu=*:-mcpu=%*} %{march=*:-march=%*}}"
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#endif /* ! GCC_ARM_H */
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@ -56,8 +56,7 @@
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#define ASM_SPEC "\
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%{mbig-endian:-EB} \
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%{mlittle-endian:-EL} \
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%{mcpu=*:-mcpu=%*} \
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%{march=*:-march=%*} \
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%(asm_cpu_spec) \
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%{mapcs-*:-mapcs-%*} \
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%(subtarget_asm_float_spec) \
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%{mthumb-interwork:-mthumb-interwork} \
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@ -61,8 +61,7 @@
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#define ASM_SPEC "\
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%{fpic|fpie: -k} %{fPIC|fPIE: -k} \
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%{mbig-endian:-EB} \
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%{mcpu=*:-mcpu=%*} \
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%{march=*:-march=%*} \
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%(arm_cpu_spec) \
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%{mapcs-float:-mfloat} \
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%{mfloat-abi=*} %{mfpu=*} \
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%{mthumb-interwork:-mthumb-interwork} \
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@ -10329,6 +10329,10 @@ assembly code. Permissible names are: @samp{arm2}, @samp{arm250},
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@samp{fa526}, @samp{fa626},
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@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}.
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@option{-mcpu=generic-@var{arch}} is also permissible, and is
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equivalent to @option{-march=@var{arch} -mtune=generic-@var{arch}}.
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See @option{-mtune} for more information.
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@item -mtune=@var{name}
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@opindex mtune
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This option is very similar to the @option{-mcpu=} option, except that
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@ -10340,6 +10344,13 @@ will generate based on the CPU specified by a @option{-mcpu=} option.
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For some ARM implementations better performance can be obtained by using
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this option.
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@option{-mtune=generic-@var{arch}} specifies that GCC should tune the
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performance for a blend of processors within architecture @var{arch}.
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The aim is to generate code that run well on the current most popular
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processors, balancing between optimizations that benefit some CPUs in the
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range, and avoiding performance pitfalls of other CPUs. The effects of
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this option may change in future GCC versions as CPU models come and go.
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@item -march=@var{name}
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@opindex march
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This specifies the name of the target ARM architecture. GCC uses this
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