revert: sse.md ("sse4_1_blendvpd"): Require "z" class XMM register for operand[3].
Revert: 2007-06-02 Uros Bizjak <ubizjak@gmail.com> * config/i386/sse.md ("sse4_1_blendvpd"): Require "z" class XMM register for operand[3]. Adjust asm template. ("sse4_1_blendvpd"): Ditto. ("sse4_1_pblendvb"): Ditto. * config/i386/i386.c (ix86_expand_sse_4_operands_builtin): Do not force operands[3] into xmm0 register for variable blend instructions. From-SVN: r125285
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@ -1,12 +1,7 @@
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2007-06-02 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/sse.md ("sse4_1_blendvpd"): Require "z" class XMM
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register for operand[3]. Adjust asm template.
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("sse4_1_blendvpd"): Ditto.
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("sse4_1_pblendvb"): Ditto.
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* config/i386/i386.c (ix86_expand_sse_4_operands_builtin): Call
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safe_vector_operand() if input operand is VECTOR_MODE_P operand. Do not
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force operands[3] into xmm0 register for variable blend instructions.
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safe_vector_operand() if input operand is VECTOR_MODE_P operand.
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(ix86_expand_sse_pcmpestr): Do not check operands for
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"register_operand", when insn operand predicate is "register_operand".
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(ix86_expand_sse_pcmpistr): Ditto.
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@ -18280,14 +18280,13 @@ ix86_expand_sse_4_operands_builtin (enum insn_code icode, tree exp,
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enum machine_mode tmode = insn_data[icode].operand[0].mode;
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enum machine_mode mode1 = insn_data[icode].operand[1].mode;
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enum machine_mode mode2 = insn_data[icode].operand[2].mode;
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enum machine_mode mode3 = insn_data[icode].operand[3].mode;
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enum machine_mode mode3;
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rtx xmm0;
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if (VECTOR_MODE_P (mode1))
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op0 = safe_vector_operand (op0, mode1);
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if (VECTOR_MODE_P (mode2))
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op1 = safe_vector_operand (op1, mode2);
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if (VECTOR_MODE_P (mode3))
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op2 = safe_vector_operand (op2, mode3);
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if (optimize
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|| target == 0
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@ -18301,24 +18300,42 @@ ix86_expand_sse_4_operands_builtin (enum insn_code icode, tree exp,
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|| !(*insn_data[icode].operand[2].predicate) (op1, mode2))
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op1 = copy_to_mode_reg (mode2, op1);
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if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
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switch (icode)
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{
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case CODE_FOR_sse4_1_blendvpd:
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case CODE_FOR_sse4_1_blendvps:
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case CODE_FOR_sse4_1_pblendvb:
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switch (icode)
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{
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case CODE_FOR_sse4_1_blendvpd:
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case CODE_FOR_sse4_1_blendvps:
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case CODE_FOR_sse4_1_pblendvb:
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mode3 = tmode;
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op2 = safe_vector_operand (op2, mode3);
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if (!register_operand (op2, mode3))
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op2 = copy_to_mode_reg (mode3, op2);
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break;
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case CODE_FOR_sse4_1_roundsd:
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case CODE_FOR_sse4_1_roundss:
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error ("the third argument must be a 4-bit immediate");
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return const0_rtx;
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/* ??? The third argument of variable blends must be xmm0. */
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xmm0 = gen_rtx_REG (mode3, XMM0_REG);
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default:
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error ("the third argument must be an 8-bit immediate");
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return const0_rtx;
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}
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emit_move_insn (xmm0, op2);
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op2 = xmm0;
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break;
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default:
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mode3 = insn_data[icode].operand[3].mode;
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if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
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{
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switch (icode)
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{
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case CODE_FOR_sse4_1_roundsd:
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case CODE_FOR_sse4_1_roundss:
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error ("the third argument must be a 4-bit immediate");
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break;
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default:
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error ("the third argument must be an 8-bit immediate");
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break;
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}
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return const0_rtx;
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}
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break;
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}
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pat = GEN_FCN (icode) (target, op0, op1, op2);
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if (! pat)
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@ -204,6 +204,7 @@
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(FLAGS_REG 17)
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(FPSR_REG 18)
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(FPCR_REG 19)
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(XMM0_REG 21)
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(R10_REG 39)
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(R11_REG 40)
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])
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@ -5844,10 +5844,10 @@
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[(set (match_operand:V2DF 0 "register_operand" "=x")
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(unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
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(match_operand:V2DF 2 "nonimmediate_operand" "xm")
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(match_operand:V2DF 3 "register_operand" "z")]
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(reg:V2DF XMM0_REG)]
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UNSPEC_BLENDV))]
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"TARGET_SSE4_1"
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"blendvpd\t{%3, %2, %0|%0, %2, %3}"
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"blendvpd\t{%%xmm0, %2, %0|%0, %2, %%xmm0}"
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[(set_attr "type" "ssemov")
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(set_attr "prefix_extra" "1")
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(set_attr "mode" "V2DF")])
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@ -5856,10 +5856,10 @@
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[(set (match_operand:V4SF 0 "register_operand" "=x")
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(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
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(match_operand:V4SF 2 "nonimmediate_operand" "xm")
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(match_operand:V4SF 3 "register_operand" "z")]
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(reg:V4SF XMM0_REG)]
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UNSPEC_BLENDV))]
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"TARGET_SSE4_1"
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"blendvps\t{%3, %2, %0|%0, %2, %3}"
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"blendvps\t{%%xmm0, %2, %0|%0, %2, %%xmm0}"
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[(set_attr "type" "ssemov")
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(set_attr "prefix_extra" "1")
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(set_attr "mode" "V4SF")])
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@ -5927,10 +5927,10 @@
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[(set (match_operand:V16QI 0 "register_operand" "=x")
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(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0")
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(match_operand:V16QI 2 "nonimmediate_operand" "xm")
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(match_operand:V16QI 3 "register_operand" "z")]
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(reg:V16QI XMM0_REG)]
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UNSPEC_BLENDV))]
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"TARGET_SSE4_1"
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"pblendvb\t{%3, %2, %0|%0, %2, %3}"
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"pblendvb\t{%%xmm0, %2, %0|%0, %2, %%xmm0}"
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[(set_attr "type" "ssemov")
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(set_attr "prefix_extra" "1")
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(set_attr "mode" "TI")])
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