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rs6000.md (movdf_hardfloat32): Handle PRE_INC and PRE_DEC the same as offsettable in cases 1 and 2.

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* rs6000.md (movdf_hardfloat32): Handle PRE_INC and PRE_DEC the
        same as offsettable in cases 1 and 2.

From-SVN: r27898
This commit is contained in:
David Edelsohn 1999-07-01 21:11:20 +00:00 committed by David Edelsohn
parent 786d609233
commit 69f51a211a
2 changed files with 11 additions and 10 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
Fri Jul 2 00:04:23 1999 David Edelsohn <edelsohn@gnu.org>
* rs6000.md (movdf_hardfloat32): Handle PRE_INC and PRE_DEC the
same as offsettable in cases 1 and 2.
Thu Jul 1 20:54:10 1999 Richard Henderson <rth@cygnus.com>
* alpha.md (extqh): Define as 64-((R&7)*8) instead of 56-(((R-1)&7)*8).

16
gcc/config/rs6000/rs6000.md
View File

@ -6329,7 +6329,9 @@
case 1:
if (offsettable_memref_p (operands[1])
|| (GET_CODE (operands[1]) == MEM
&& GET_CODE (XEXP (operands[1], 0)) == LO_SUM))
&& (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
|| GET_CODE (XEXP (operands[1], 0)) == PRE_INC
|| GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
{
/* If the low-address word is used in the address, we must load
it last. Otherwise, load it first. Note that we cannot have
@ -6345,10 +6347,6 @@
{
rtx addreg;
if (GET_CODE (XEXP (operands[1], 0)) == PRE_INC
|| GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
abort ();
addreg = find_addr_reg (XEXP (operands[1], 0));
if (refers_to_regno_p (REGNO (operands[0]),
REGNO (operands[0]) + 1,
@ -6371,16 +6369,14 @@
case 2:
if (offsettable_memref_p (operands[0])
|| (GET_CODE (operands[0]) == MEM
&& GET_CODE (XEXP (operands[0], 0)) == LO_SUM))
&& (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
|| GET_CODE (XEXP (operands[0], 0)) == PRE_INC
|| GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
else
{
rtx addreg;
if (GET_CODE (XEXP (operands[0], 0)) == PRE_INC
|| GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
abort ();
addreg = find_addr_reg (XEXP (operands[0], 0));
output_asm_insn (\"{stx|stwx} %1,%0\", operands);
output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);