mips.h (MASK_FIX_SB1): Bump.
* config/mips/mips.h (MASK_FIX_SB1): Bump. (MASK_FIX_R4400, TARGET_FIX_R4400): New macros. (TARGET_SWITCHES): Add -mfix-r4400 and -mno-fix-r4400. * config/mips/mips.c (mips_output_division): Fill the branch delay slot with a nop if TARGET_FIX_R4000. Extend R4000 workarounds to TARGET_FIX_R4400. (mips_output_division): Adjust accordingly. (override_options): Make -march=r4400 imply -mfix-r4400 by default. * doc/invoke.texi: Document -mfix-r4400 and new errata workarounds. Co-Authored-By: Richard Sandiford <rsandifo@redhat.com> From-SVN: r78825
This commit is contained in:
Maciej W. Rozycki
Richard Sandiford
parent
ec8e098d3d
commit
6ba7b54780
@ -1,3 +1,16 @@
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2004-03-03 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
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Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips.h (MASK_FIX_SB1): Bump.
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(MASK_FIX_R4400, TARGET_FIX_R4400): New macros.
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(TARGET_SWITCHES): Add -mfix-r4400 and -mno-fix-r4400.
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* config/mips/mips.c (mips_output_division): Fill the branch delay
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slot with a nop if TARGET_FIX_R4000. Extend R4000 workarounds to
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TARGET_FIX_R4400.
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(mips_output_division): Adjust accordingly.
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(override_options): Make -march=r4400 imply -mfix-r4400 by default.
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* doc/invoke.texi: Document -mfix-r4400 and new errata workarounds.
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2004-03-03 Paolo Bonzini <bonzini@gnu.org>
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* alias.c (rtx_equal_for_memref_p): Use predicates
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@ -1321,7 +1321,7 @@ mips_idiv_insns (void)
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count = 1;
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if (TARGET_CHECK_ZERO_DIV)
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count += 2;
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if (TARGET_FIX_R4000)
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if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
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count++;
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return count;
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}
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@ -5101,6 +5101,12 @@ override_options (void)
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if ((target_flags_explicit & MASK_FIX_R4000) == 0
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&& mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
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target_flags |= MASK_FIX_R4000;
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/* Default to working around R4400 errata only if the processor
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was selected explicitly. */
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if ((target_flags_explicit & MASK_FIX_R4400) == 0
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&& mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
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target_flags |= MASK_FIX_R4400;
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}
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/* Implement CONDITIONAL_REGISTER_USAGE. */
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@ -9171,19 +9177,94 @@ mips_output_conditional_branch (rtx insn, rtx *operands, int two_operands_p,
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return 0;
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}
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/* Used to output div or ddiv instruction DIVISION, which has the
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operands given by OPERANDS. If we need a divide-by-zero check,
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output the instruction and return an asm string that traps if
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operand 2 is zero.
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/* Used to output div or ddiv instruction DIVISION, which has the operands
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given by OPERANDS. Add in a divide-by-zero check if needed.
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The original R4000 has a cpu bug. If a double-word or a variable
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shift executes immediately after starting an integer division, the
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shift may give an incorrect result. Avoid this by adding a nop on
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the R4000. See quotations of errata #16 and #28 from "MIPS
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R4000PC/SC Errata, Processor Revision 2.2 and 3.0" in mips.md for
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details.
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When working around R4000 and R4400 errata, we need to make sure that
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the division is not immediately followed by a shift[1][2]. We also
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need to stop the division from being put into a branch delay slot[3].
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The easiest way to avoid both problems is to add a nop after the
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division. When a divide-by-zero check is neeeded, this nop can be
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used to fill the branch delay slot.
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Otherwise just return DIVISION itself. */
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[1] If a double-word or a variable shift executes immediately
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after starting an integer division, the shift may give an
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incorrect result. See quotations of errata #16 and #28 from
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"MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
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in mips.md for details.
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[2] A similar bug to [1] exists for all revisions of the
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R4000 and the R4400 when run in an MC configuration.
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From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
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"19. In this following sequence:
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ddiv (or ddivu or div or divu)
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dsll32 (or dsrl32, dsra32)
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if an MPT stall occurs, while the divide is slipping the cpu
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pipeline, then the following double shift would end up with an
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incorrect result.
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Workaround: The compiler needs to avoid generating any
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sequence with divide followed by extended double shift."
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This erratum is also present in "MIPS R4400MC Errata, Processor
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Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
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& 3.0" as errata #10 and #4, respectively.
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[3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
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(also valid for MIPS R4000MC processors):
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"52. R4000SC: This bug does not apply for the R4000PC.
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There are two flavors of this bug:
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1) If the instruction just after divide takes an RF exception
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(tlb-refill, tlb-invalid) and gets an instruction cache
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miss (both primary and secondary) and the line which is
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currently in secondary cache at this index had the first
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data word, where the bits 5..2 are set, then R4000 would
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get a wrong result for the div.
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##1
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nop
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div r8, r9
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------------------- # end-of page. -tlb-refill
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nop
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##2
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nop
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div r8, r9
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------------------- # end-of page. -tlb-invalid
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nop
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2) If the divide is in the taken branch delay slot, where the
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target takes RF exception and gets an I-cache miss for the
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exception vector or where I-cache miss occurs for the
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target address, under the above mentioned scenarios, the
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div would get wrong results.
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##1
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j r2 # to next page mapped or unmapped
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div r8,r9 # this bug would be there as long
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# as there is an ICache miss and
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nop # the "data pattern" is present
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##2
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beq r0, r0, NextPage # to Next page
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div r8,r9
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nop
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This bug is present for div, divu, ddiv, and ddivu
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instructions.
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Workaround: For item 1), OS could make sure that the next page
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after the divide instruction is also mapped. For item 2), the
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compiler could make sure that the divide instruction is not in
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the branch delay slot."
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These processors have PRId values of 0x00004220 and 0x00004300 for
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the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
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const char *
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mips_output_division (const char *division, rtx *operands)
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@ -9191,6 +9272,11 @@ mips_output_division (const char *division, rtx *operands)
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const char *s;
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s = division;
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if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
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{
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output_asm_insn (s, operands);
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s = "nop";
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}
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if (TARGET_CHECK_ZERO_DIV)
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{
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if (TARGET_MIPS16)
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@ -9205,11 +9291,6 @@ mips_output_division (const char *division, rtx *operands)
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s = "break\t7%)\n1:";
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}
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}
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if (TARGET_FIX_R4000)
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{
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output_asm_insn (s, operands);
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s = "nop";
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}
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return s;
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}
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@ -170,7 +170,8 @@ extern const struct mips_cpu_info *mips_tune_info;
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0x00800000 /* Store uninitialized
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consts in rodata */
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#define MASK_FIX_R4000 0x01000000 /* Work around R4000 errata. */
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#define MASK_FIX_SB1 0x02000000 /* Work around SB-1 errata. */
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#define MASK_FIX_R4400 0x02000000 /* Work around R4400 errata. */
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#define MASK_FIX_SB1 0x04000000 /* Work around SB-1 errata. */
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/* Debug switches, not documented */
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#define MASK_DEBUG 0 /* unused */
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@ -252,6 +253,9 @@ extern const struct mips_cpu_info *mips_tune_info;
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/* Work around R4000 errata. */
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#define TARGET_FIX_R4000 (target_flags & MASK_FIX_R4000)
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/* Work around R4400 errata. */
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#define TARGET_FIX_R4400 (target_flags & MASK_FIX_R4400)
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/* True if we should use NewABI-style relocation operators for
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symbolic addresses. This is never true for mips16 code,
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which has its own conventions. */
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@ -596,6 +600,10 @@ extern const struct mips_cpu_info *mips_tune_info;
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N_("Work around R4000 errata")}, \
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{"no-fix-r4000", -MASK_FIX_R4000, \
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N_("Don't work around R4000 errata")}, \
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{"fix-r4400", MASK_FIX_R4400, \
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N_("Work around R4400 errata")}, \
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{"no-fix-r4400", -MASK_FIX_R4400, \
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N_("Don't work around R4400 errata")}, \
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{"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
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N_("Trap on integer divide by zero")}, \
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{"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
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@ -478,7 +478,8 @@ in the following sections.
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-mcheck-zero-division -mno-check-zero-division @gol
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-mmemcpy -mno-memcpy -mlong-calls -mno-long-calls @gol
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-mmad -mno-mad -mfused-madd -mno-fused-madd -nocpp @gol
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-mfix-r4000 -mno-fix-r4000 -mfix-sb1 -mno-fix-sb1 @gol
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-mfix-r4000 -mno-fix-r4000 -mfix-r4400 -mno-fix-r4400 @gol
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-mfix-sb1 -mno-fix-sb1 @gol
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-mflush-func=@var{func} -mno-flush-func @gol
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-mbranch-likely -mno-branch-likely}
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@ -8048,6 +8049,20 @@ immediately after starting an integer division.
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@item
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A double-word or a variable shift may give an incorrect result if executed
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while an integer multiplication is in progress.
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@item
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An integer division may give an incorrect result if started in a delay slot
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of a taken branch or a jump.
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@end itemize
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@item -mfix-r4400
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@itemx -mno-fix-r4400
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@opindex mfix-r4400
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@opindex mno-fix-r4400
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Work around certain R4400 CPU errata:
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@itemize @minus
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@item
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A double-word or a variable shift may give an incorrect result if executed
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immediately after starting an integer division.
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@end itemize
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@item -mfix-sb1
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