[ARM][trivial] Use uppercase for code iterator names
* config/arm/iterators.md (shiftable_ops): Rename to... (SHIFTABLE_OPS): ... This. Update use in comments. (ior_xor): Rename to... (IOR_XOR): ... This. (vqh_ops): Rename to... (VQH_OPS): ... This. (vqhs_ops): Rename to... (VQHS_OPS): ... This. (rshifts): Rename to... (RSHIFTS): ... This. (returns): Rename to... (RETURNS): ... This. * config/arm/arm.md: Update uses of the above. * config/arm/neon.md: Likewise. From-SVN: r222416
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2015-04-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/arm/iterators.md (shiftable_ops): Rename to...
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(SHIFTABLE_OPS): ... This. Update use in comments.
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(ior_xor): Rename to...
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(IOR_XOR): ... This.
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(vqh_ops): Rename to...
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(VQH_OPS): ... This.
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(vqhs_ops): Rename to...
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(VQHS_OPS): ... This.
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(rshifts): Rename to...
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(RSHIFTS): ... This.
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(returns): Rename to...
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(RETURNS): ... This.
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* config/arm/arm.md: Update uses of the above.
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* config/arm/neon.md: Likewise.
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2014-04-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config.host (case ${host}): Add aarch64*-*-linux case.
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@ -5076,7 +5076,7 @@
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(define_split
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[(set (match_operand:SI 0 "s_register_operand" "")
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(ior_xor:SI (and:SI (ashift:SI
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(IOR_XOR:SI (and:SI (ashift:SI
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(match_operand:SI 1 "s_register_operand" "")
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(match_operand:SI 2 "const_int_operand" ""))
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(match_operand:SI 3 "const_int_operand" ""))
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@ -5088,7 +5088,7 @@
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== (GET_MODE_MASK (GET_MODE (operands[5]))
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& (GET_MODE_MASK (GET_MODE (operands[5]))
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<< (INTVAL (operands[2])))))"
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[(set (match_dup 0) (ior_xor:SI (ashift:SI (match_dup 1) (match_dup 2))
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[(set (match_dup 0) (IOR_XOR:SI (ashift:SI (match_dup 1) (match_dup 2))
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(match_dup 4)))
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(set (match_dup 0) (zero_extend:SI (match_dup 5)))]
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"operands[5] = gen_lowpart (GET_MODE (operands[5]), operands[0]);"
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@ -7848,7 +7848,7 @@
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)
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(define_expand "<return_str>return"
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[(returns)]
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[(RETURNS)]
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"(TARGET_ARM || (TARGET_THUMB2
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&& ARM_FUNC_TYPE (arm_current_func_type ()) == ARM_FT_NORMAL
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&& !IS_STACKALIGN (arm_current_func_type ())))
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@ -7886,7 +7886,7 @@
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[(set (pc)
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(if_then_else (match_operator 0 "arm_comparison_operator"
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[(match_operand 1 "cc_register" "") (const_int 0)])
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(returns)
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(RETURNS)
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(pc)))]
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"TARGET_ARM <return_cond_true>"
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"*
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@ -7909,7 +7909,7 @@
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(if_then_else (match_operator 0 "arm_comparison_operator"
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[(match_operand 1 "cc_register" "") (const_int 0)])
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(pc)
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(returns)))]
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(RETURNS)))]
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"TARGET_ARM <return_cond_true>"
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"*
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{
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@ -8243,7 +8243,7 @@
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(define_insn "*<arith_shift_insn>_multsi"
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[(set (match_operand:SI 0 "s_register_operand" "=r,r")
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(shiftable_ops:SI
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(SHIFTABLE_OPS:SI
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(mult:SI (match_operand:SI 2 "s_register_operand" "r,r")
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(match_operand:SI 3 "power_of_two_operand" ""))
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(match_operand:SI 1 "s_register_operand" "rk,<t2_binop0>")))]
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@ -8257,7 +8257,7 @@
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(define_insn "*<arith_shift_insn>_shiftsi"
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[(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
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(shiftable_ops:SI
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(SHIFTABLE_OPS:SI
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(match_operator:SI 2 "shift_nomul_operator"
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[(match_operand:SI 3 "s_register_operand" "r,r,r")
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(match_operand:SI 4 "shift_amount_operand" "M,M,r")])
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@ -191,34 +191,34 @@
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(define_code_iterator COMPARISONS [eq gt ge le lt])
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;; A list of ...
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(define_code_iterator ior_xor [ior xor])
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(define_code_iterator IOR_XOR [ior xor])
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;; Operations on two halves of a quadword vector.
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(define_code_iterator vqh_ops [plus smin smax umin umax])
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(define_code_iterator VQH_OPS [plus smin smax umin umax])
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;; Operations on two halves of a quadword vector,
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;; without unsigned variants (for use with *SFmode pattern).
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(define_code_iterator vqhs_ops [plus smin smax])
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(define_code_iterator VQHS_OPS [plus smin smax])
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;; A list of widening operators
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(define_code_iterator SE [sign_extend zero_extend])
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;; Right shifts
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(define_code_iterator rshifts [ashiftrt lshiftrt])
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(define_code_iterator RSHIFTS [ashiftrt lshiftrt])
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;; Iterator for integer conversions
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(define_code_iterator FIXUORS [fix unsigned_fix])
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;; Binary operators whose second operand can be shifted.
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(define_code_iterator shiftable_ops [plus minus ior xor and])
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(define_code_iterator SHIFTABLE_OPS [plus minus ior xor and])
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;; plus and minus are the only shiftable_ops for which Thumb2 allows
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;; plus and minus are the only SHIFTABLE_OPS for which Thumb2 allows
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;; a stack pointer opoerand. The minus operation is a candidate for an rsub
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;; and hence only plus is supported.
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(define_code_attr t2_binop0
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[(plus "rk") (minus "r") (ior "r") (xor "r") (and "r")])
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;; The instruction to use when a shiftable_ops has a shift operation as
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;; The instruction to use when a SHIFTABLE_OPS has a shift operation as
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;; its first operand.
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(define_code_attr arith_shift_insn
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[(plus "add") (minus "rsb") (ior "orr") (xor "eor") (and "and")])
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@ -797,7 +797,7 @@
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(UNSPEC_SHA256H2 "V4SI") (UNSPEC_SHA256SU1 "V4SI")])
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;; Both kinds of return insn.
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(define_code_iterator returns [return simple_return])
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(define_code_iterator RETURNS [return simple_return])
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(define_code_attr return_str [(return "") (simple_return "simple_")])
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(define_code_attr return_simple_p [(return "false") (simple_return "true")])
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(define_code_attr return_cond_false [(return " && USE_RETURN_INSN (FALSE)")
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@ -1114,7 +1114,7 @@
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;; lshrdi3_neon
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(define_insn_and_split "<shift>di3_neon"
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[(set (match_operand:DI 0 "s_register_operand" "= w, w,?&r,?r,?w,?w")
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(rshifts:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, r,0w, w")
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(RSHIFTS:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, r,0w, w")
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(match_operand:SI 2 "reg_or_int_operand" " r, i, r, i, r, i")))
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(clobber (match_scratch:SI 3 "=2r, X, &r, X,2r, X"))
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(clobber (match_scratch:SI 4 "= X, X, &r, X, X, X"))
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@ -1267,7 +1267,7 @@
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(define_insn "quad_halves_<code>v4si"
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[(set (match_operand:V2SI 0 "s_register_operand" "=w")
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(vqh_ops:V2SI
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(VQH_OPS:V2SI
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(vec_select:V2SI (match_operand:V4SI 1 "s_register_operand" "w")
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(parallel [(const_int 0) (const_int 1)]))
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(vec_select:V2SI (match_dup 1)
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@ -1280,7 +1280,7 @@
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(define_insn "quad_halves_<code>v4sf"
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[(set (match_operand:V2SF 0 "s_register_operand" "=w")
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(vqhs_ops:V2SF
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(VQHS_OPS:V2SF
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(vec_select:V2SF (match_operand:V4SF 1 "s_register_operand" "w")
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(parallel [(const_int 0) (const_int 1)]))
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(vec_select:V2SF (match_dup 1)
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@ -1293,7 +1293,7 @@
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(define_insn "quad_halves_<code>v8hi"
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[(set (match_operand:V4HI 0 "s_register_operand" "+w")
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(vqh_ops:V4HI
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(VQH_OPS:V4HI
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(vec_select:V4HI (match_operand:V8HI 1 "s_register_operand" "w")
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(parallel [(const_int 0) (const_int 1)
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(const_int 2) (const_int 3)]))
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@ -1308,7 +1308,7 @@
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(define_insn "quad_halves_<code>v16qi"
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[(set (match_operand:V8QI 0 "s_register_operand" "+w")
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(vqh_ops:V8QI
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(VQH_OPS:V8QI
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(vec_select:V8QI (match_operand:V16QI 1 "s_register_operand" "w")
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(parallel [(const_int 0) (const_int 1)
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(const_int 2) (const_int 3)
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