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rs6000.c: Add case statement entry to make the xvcvuxdsp built-in argument unsigned. 

gcc/ChangeLog:

2017-02-14  Carl Love  <cel@us.ibm.com>

	* config/rs6000/rs6000.c: Add case statement entry to make the
	xvcvuxdsp built-in argument unsigned.
	* config/rs6000/vsx.md: Fix the source and return operand types so they
	match the instruction definitions from the ISA document.  Fix typo
	in the instruction generation for the (define_insn "vsx_xvcvuxdsp"
	statement.

gcc/testsuite/ChangeLog:

2017-01-14  Carl Love  <cel@us.ibm.com>

	* gcc.target/powerpc/vsx-builtin-3.c: Add missing test case for the
	xvcvsxdsp and xvcvuxdsp instructions.

From-SVN: r245460
This commit is contained in:
Carl Love 2017-02-14 23:11:19 +00:00 committed by Carl Love
parent 584898ee80
commit 8722316bd6
5 changed files with 43 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
gcc/ChangeLog
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@ -1,3 +1,12 @@
2017-02-14 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000.c: Add case statement entry to make the
xvcvuxdsp built-in argument unsigned.
* config/rs6000/vsx.md: Fix the source and return operand types so they
match the instruction definitions from the ISA document. Fix typo
in the instruction generation for the (define_insn "vsx_xvcvuxdsp"
statement.
2017-02-14 Vladimir Makarov <vmakarov@redhat.com>
PR target/79282

1
gcc/config/rs6000/rs6000.c
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@ -18594,6 +18594,7 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
break;
/* unsigned args, signed return. */
case VSX_BUILTIN_XVCVUXDSP:
case VSX_BUILTIN_XVCVUXDDP_UNS:
case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
h.uns_p[1] = 1;

10
gcc/config/rs6000/vsx.md
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@ -1914,19 +1914,19 @@
[(set_attr "type" "vecdouble")])
(define_insn "vsx_xvcvsxdsp"
[(set (match_operand:V4SI 0 "vsx_register_operand" "=wd,?wa")
(unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wf,wa")]
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wd,?wa")
(unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wf,wa")]
UNSPEC_VSX_CVSXDSP))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"xvcvsxdsp %x0,%x1"
[(set_attr "type" "vecfloat")])
(define_insn "vsx_xvcvuxdsp"
[(set (match_operand:V4SI 0 "vsx_register_operand" "=wd,?wa")
(unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wf,wa")]
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wd,?wa")
(unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wf,wa")]
UNSPEC_VSX_CVUXDSP))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"xvcvuxwdp %x0,%x1"
"xvcvuxdsp %x0,%x1"
[(set_attr "type" "vecdouble")])
;; Convert from 32-bit to 64-bit types

5
gcc/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2017-01-14 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/vsx-builtin-3.c: Add missing test case for the
xvcvsxdsp and xvcvuxdsp instructions.
2017-02-14 Segher Boessenkool <segher@kernel.crashing.org>
* gcc.target/powerpc/vec-adde-int128.c: Only run if int128 exists.

23
gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
View File

@ -35,6 +35,8 @@
/* { dg-final { scan-assembler "xvcmpgesp" } } */
/* { dg-final { scan-assembler "xxsldwi" } } */
/* { dg-final { scan-assembler-not "call" } } */
/* { dg-final { scan-assembler "xvcvsxdsp" } } */
/* { dg-final { scan-assembler "xvcvuxdsp" } } */
extern __vector int si[][4];
extern __vector short ss[][4];
@ -50,7 +52,9 @@ extern __vector __pixel p[][4];
#ifdef __VSX__
extern __vector double d[][4];
extern __vector long sl[][4];
extern __vector long long sll[][4];
extern __vector unsigned long ul[][4];
extern __vector unsigned long long ull[][4];
extern __vector __bool long bl[][4];
#endif
@ -211,3 +215,22 @@ int do_xxsldwi (void)
d[i][0] = __builtin_vsx_xxsldwi (d[i][1], d[i][2], 3); i++;
return i;
}
int do_xvcvsxdsp (void)
{
int i = 0;
f[i][0] = __builtin_vsx_xvcvsxdsp (sll[i][1]); i++;
return i;
}
int do_xvcvuxdsp (void)
{
int i = 0;
f[i][0] = __builtin_vsx_xvcvuxdsp (ull[i][1]); i++;
return i;
}