[AArch64] Use unspecs for SVE conversions involving floats
This patch changes the SVE FP<->FP and FP<->INT patterns so that they use unspecs rather than rtx codes, continuing the series to make the patterns work with predicates that might not be all-true. 2019-08-14 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64.md (UNSPEC_FLOAT_CONVERT): Delete. * config/aarch64/iterators.md (UNSPEC_COND_FCVT, UNSPEC_COND_FCVTZS) (UNSPEC_COND_FCVTZU, UNSPEC_COND_SCVTF, UNSPEC_COND_UCVTF): New unspecs. (optab, su): Handle them. (SVE_COND_FCVTI, SVE_COND_ICVTF): New int iterators. * config/aarch64/aarch64-sve.md (<fix_trunc_optab><SVE_F:mode><v_int_equiv>2): Replace with... (<SVE_COND_FCVTI:optab><SVE_F:mode><v_int_equiv>2): ...this. (*<fix_trunc_optab>v16hsf<:SVE_HSDImode>2): Replace with... (*<SVE_COND_FCVTI:optab>v16hsf<SVE_F:mode>2): ...this. (*<fix_trunc_optab>vnx4sf<SVE_SDI:mode>2): Replace with... (*<SVE_COND_FCVTI:optab>vnx4sf<SVE_SDI:mode>2): ...this. (*<fix_trunc_optab>vnx2df<SVE_SDI:mode>2): Replace with... (*<SVE_COND_FCVTI:optab>vnx2df<SVE_SDI:mode>2): ...this. (vec_pack_<su>fix_trunc_vnx2df): Use SVE_COND_FCVTI instead of FIXUORS. (<FLOATUORS:optab><v_int_equiv><SVE_F:mode>2): Replace with... (<SVE_COND_ICVTF:optab><v_int_equiv><SVE_F:mode>2): ...this. (*<FLOATUORS:optab><SVE_HSDI:mode>vnx8hf2): Replace with... (*<SVE_COND_ICVTF:optab><SVE_HSDI:mode>vnx8hf2): ...this. (*<FLOATUORS:optab><SVE_SDI:mode>vnx4sf2): Replace with... (*<SVE_COND_ICVTF:optab><SVE_SDI:mode>vnx4sf2): ...this. (aarch64_sve_<FLOATUORS:optab><SVE_SDI:mode>vnx2df2): Replace with... (aarch64_sve_<SVE_COND_ICVTF:optab><SVE_SDI:mode>vnx2df2): ...this. (vec_unpack<su_optab>_float_<perm_hilo>_vnx4si): Pass a GP strictness operand to aarch64_sve_<SVE_COND_ICVTF:optab><SVE_SDI:mode>vnx2df2. (vec_pack_trunc_<SVE_HSF:Vwide>, *trunc<Vwide><SVE_HSF:mode>2) (aarch64_sve_extend<mode><Vwide>2): Use UNSPEC_COND_FCVT instead of UNSPEC_FLOAT_CONVERT. (vec_unpacks_<perm_hilo>_<mode>): Pass a GP strictness operand to aarch64_sve_extend<mode><Vwide>2. From-SVN: r274423
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
c6521daac8
commit
9936155162
@ -1,3 +1,38 @@
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2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64.md (UNSPEC_FLOAT_CONVERT): Delete.
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* config/aarch64/iterators.md (UNSPEC_COND_FCVT, UNSPEC_COND_FCVTZS)
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(UNSPEC_COND_FCVTZU, UNSPEC_COND_SCVTF, UNSPEC_COND_UCVTF): New
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unspecs.
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(optab, su): Handle them.
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(SVE_COND_FCVTI, SVE_COND_ICVTF): New int iterators.
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* config/aarch64/aarch64-sve.md
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(<fix_trunc_optab><SVE_F:mode><v_int_equiv>2): Replace with...
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(<SVE_COND_FCVTI:optab><SVE_F:mode><v_int_equiv>2): ...this.
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(*<fix_trunc_optab>v16hsf<:SVE_HSDImode>2): Replace with...
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(*<SVE_COND_FCVTI:optab>v16hsf<SVE_F:mode>2): ...this.
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(*<fix_trunc_optab>vnx4sf<SVE_SDI:mode>2): Replace with...
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(*<SVE_COND_FCVTI:optab>vnx4sf<SVE_SDI:mode>2): ...this.
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(*<fix_trunc_optab>vnx2df<SVE_SDI:mode>2): Replace with...
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(*<SVE_COND_FCVTI:optab>vnx2df<SVE_SDI:mode>2): ...this.
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(vec_pack_<su>fix_trunc_vnx2df): Use SVE_COND_FCVTI instead of
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FIXUORS.
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(<FLOATUORS:optab><v_int_equiv><SVE_F:mode>2): Replace with...
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(<SVE_COND_ICVTF:optab><v_int_equiv><SVE_F:mode>2): ...this.
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(*<FLOATUORS:optab><SVE_HSDI:mode>vnx8hf2): Replace with...
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(*<SVE_COND_ICVTF:optab><SVE_HSDI:mode>vnx8hf2): ...this.
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(*<FLOATUORS:optab><SVE_SDI:mode>vnx4sf2): Replace with...
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(*<SVE_COND_ICVTF:optab><SVE_SDI:mode>vnx4sf2): ...this.
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(aarch64_sve_<FLOATUORS:optab><SVE_SDI:mode>vnx2df2): Replace with...
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(aarch64_sve_<SVE_COND_ICVTF:optab><SVE_SDI:mode>vnx2df2): ...this.
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(vec_unpack<su_optab>_float_<perm_hilo>_vnx4si): Pass a GP strictness
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operand to aarch64_sve_<SVE_COND_ICVTF:optab><SVE_SDI:mode>vnx2df2.
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(vec_pack_trunc_<SVE_HSF:Vwide>, *trunc<Vwide><SVE_HSF:mode>2)
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(aarch64_sve_extend<mode><Vwide>2): Use UNSPEC_COND_FCVT instead
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of UNSPEC_FLOAT_CONVERT.
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(vec_unpacks_<perm_hilo>_<mode>): Pass a GP strictness operand to
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aarch64_sve_extend<mode><Vwide>2.
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2019-08-14 Richard Biener <rguenther@suse.de>
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PR target/91154
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@ -3643,13 +3643,13 @@
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;; Unpredicated conversion of floats to integers of the same size (HF to HI,
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;; SF to SI or DF to DI).
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(define_expand "<fix_trunc_optab><mode><v_int_equiv>2"
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(define_expand "<optab><mode><v_int_equiv>2"
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[(set (match_operand:<V_INT_EQUIV> 0 "register_operand")
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(unspec:<V_INT_EQUIV>
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[(match_dup 2)
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(FIXUORS:<V_INT_EQUIV>
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(match_operand:SVE_F 1 "register_operand"))]
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UNSPEC_MERGE_PTRUE))]
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(const_int SVE_RELAXED_GP)
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(match_operand:SVE_F 1 "register_operand")]
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SVE_COND_FCVTI))]
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"TARGET_SVE"
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{
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operands[2] = aarch64_ptrue_reg (<VPRED>mode);
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@ -3657,37 +3657,37 @@
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)
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;; Conversion of SF to DI, SI or HI, predicated with a PTRUE.
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(define_insn "*<fix_trunc_optab>v16hsf<mode>2"
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(define_insn "*<optab>v16hsf<mode>2"
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[(set (match_operand:SVE_HSDI 0 "register_operand" "=w")
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(unspec:SVE_HSDI
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[(match_operand:<VPRED> 1 "register_operand" "Upl")
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(FIXUORS:SVE_HSDI
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(match_operand:VNx8HF 2 "register_operand" "w"))]
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UNSPEC_MERGE_PTRUE))]
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(match_operand:SI 3 "aarch64_sve_gp_strictness")
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(match_operand:VNx8HF 2 "register_operand" "w")]
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SVE_COND_FCVTI))]
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"TARGET_SVE"
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"fcvtz<su>\t%0.<Vetype>, %1/m, %2.h"
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)
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;; Conversion of SF to DI or SI, predicated with a PTRUE.
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(define_insn "*<fix_trunc_optab>vnx4sf<mode>2"
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(define_insn "*<optab>vnx4sf<mode>2"
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[(set (match_operand:SVE_SDI 0 "register_operand" "=w")
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(unspec:SVE_SDI
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[(match_operand:<VPRED> 1 "register_operand" "Upl")
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(FIXUORS:SVE_SDI
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(match_operand:VNx4SF 2 "register_operand" "w"))]
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UNSPEC_MERGE_PTRUE))]
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(match_operand:SI 3 "aarch64_sve_gp_strictness")
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(match_operand:VNx4SF 2 "register_operand" "w")]
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SVE_COND_FCVTI))]
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"TARGET_SVE"
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"fcvtz<su>\t%0.<Vetype>, %1/m, %2.s"
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)
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;; Conversion of DF to DI or SI, predicated with a PTRUE.
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(define_insn "*<fix_trunc_optab>vnx2df<mode>2"
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(define_insn "*<optab>vnx2df<mode>2"
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[(set (match_operand:SVE_SDI 0 "register_operand" "=w")
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(unspec:SVE_SDI
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[(match_operand:VNx2BI 1 "register_operand" "Upl")
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(FIXUORS:SVE_SDI
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(match_operand:VNx2DF 2 "register_operand" "w"))]
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UNSPEC_MERGE_PTRUE))]
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(match_operand:SI 3 "aarch64_sve_gp_strictness")
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(match_operand:VNx2DF 2 "register_operand" "w")]
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SVE_COND_FCVTI))]
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"TARGET_SVE"
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"fcvtz<su>\t%0.<Vetype>, %1/m, %2.d"
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)
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@ -3703,13 +3703,15 @@
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[(set (match_dup 4)
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(unspec:VNx4SI
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[(match_dup 3)
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(FIXUORS:VNx4SI (match_operand:VNx2DF 1 "register_operand"))]
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UNSPEC_MERGE_PTRUE))
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(const_int SVE_RELAXED_GP)
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(match_operand:VNx2DF 1 "register_operand")]
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SVE_COND_FCVTI))
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(set (match_dup 5)
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(unspec:VNx4SI
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[(match_dup 3)
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(FIXUORS:VNx4SI (match_operand:VNx2DF 2 "register_operand"))]
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UNSPEC_MERGE_PTRUE))
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(const_int SVE_RELAXED_GP)
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(match_operand:VNx2DF 2 "register_operand")]
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SVE_COND_FCVTI))
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(set (match_operand:VNx4SI 0 "register_operand")
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(unspec:VNx4SI [(match_dup 4) (match_dup 5)] UNSPEC_UZP1))]
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"TARGET_SVE"
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@ -3740,9 +3742,9 @@
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[(set (match_operand:SVE_F 0 "register_operand")
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(unspec:SVE_F
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[(match_dup 2)
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(FLOATUORS:SVE_F
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(match_operand:<V_INT_EQUIV> 1 "register_operand"))]
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UNSPEC_MERGE_PTRUE))]
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(const_int SVE_RELAXED_GP)
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(match_operand:<V_INT_EQUIV> 1 "register_operand")]
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SVE_COND_ICVTF))]
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"TARGET_SVE"
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{
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operands[2] = aarch64_ptrue_reg (<VPRED>mode);
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@ -3755,11 +3757,11 @@
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[(set (match_operand:VNx8HF 0 "register_operand" "=w")
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(unspec:VNx8HF
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[(match_operand:<VPRED> 1 "register_operand" "Upl")
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(FLOATUORS:VNx8HF
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(match_operand:SVE_HSDI 2 "register_operand" "w"))]
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UNSPEC_MERGE_PTRUE))]
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(match_operand:SI 3 "aarch64_sve_gp_strictness")
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(match_operand:SVE_HSDI 2 "register_operand" "w")]
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SVE_COND_ICVTF))]
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"TARGET_SVE"
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"<su_optab>cvtf\t%0.h, %1/m, %2.<Vetype>"
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"<su>cvtf\t%0.h, %1/m, %2.<Vetype>"
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)
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;; Conversion of DI or SI to the same number of SFs, predicated with a PTRUE.
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@ -3767,11 +3769,11 @@
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[(set (match_operand:VNx4SF 0 "register_operand" "=w")
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(unspec:VNx4SF
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[(match_operand:<VPRED> 1 "register_operand" "Upl")
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(FLOATUORS:VNx4SF
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(match_operand:SVE_SDI 2 "register_operand" "w"))]
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UNSPEC_MERGE_PTRUE))]
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(match_operand:SI 3 "aarch64_sve_gp_strictness")
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(match_operand:SVE_SDI 2 "register_operand" "w")]
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SVE_COND_ICVTF))]
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"TARGET_SVE"
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"<su_optab>cvtf\t%0.s, %1/m, %2.<Vetype>"
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"<su>cvtf\t%0.s, %1/m, %2.<Vetype>"
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)
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;; Conversion of DI or SI to DF, predicated with a PTRUE.
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@ -3779,11 +3781,11 @@
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[(set (match_operand:VNx2DF 0 "register_operand" "=w")
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(unspec:VNx2DF
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[(match_operand:VNx2BI 1 "register_operand" "Upl")
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(FLOATUORS:VNx2DF
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(match_operand:SVE_SDI 2 "register_operand" "w"))]
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UNSPEC_MERGE_PTRUE))]
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(match_operand:SI 3 "aarch64_sve_gp_strictness")
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(match_operand:SVE_SDI 2 "register_operand" "w")]
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SVE_COND_ICVTF))]
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"TARGET_SVE"
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"<su_optab>cvtf\t%0.d, %1/m, %2.<Vetype>"
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"<su>cvtf\t%0.d, %1/m, %2.<Vetype>"
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)
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;; -------------------------------------------------------------------------
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@ -3818,8 +3820,9 @@
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: gen_aarch64_sve_zip1vnx4si)
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(temp, operands[1], operands[1]));
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rtx ptrue = aarch64_ptrue_reg (VNx2BImode);
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emit_insn (gen_aarch64_sve_<FLOATUORS:optab>vnx4sivnx2df2 (operands[0],
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ptrue, temp));
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rtx strictness = gen_int_mode (SVE_RELAXED_GP, SImode);
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emit_insn (gen_aarch64_sve_<FLOATUORS:optab>vnx4sivnx2df2
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(operands[0], ptrue, temp, strictness));
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DONE;
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}
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)
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@ -3837,15 +3840,15 @@
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[(set (match_dup 4)
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(unspec:SVE_HSF
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[(match_dup 3)
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(unspec:SVE_HSF [(match_operand:<VWIDE> 1 "register_operand")]
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UNSPEC_FLOAT_CONVERT)]
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UNSPEC_MERGE_PTRUE))
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(const_int SVE_RELAXED_GP)
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(match_operand:<VWIDE> 1 "register_operand")]
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UNSPEC_COND_FCVT))
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(set (match_dup 5)
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(unspec:SVE_HSF
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[(match_dup 3)
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(unspec:SVE_HSF [(match_operand:<VWIDE> 2 "register_operand")]
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UNSPEC_FLOAT_CONVERT)]
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UNSPEC_MERGE_PTRUE))
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(const_int SVE_RELAXED_GP)
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(match_operand:<VWIDE> 2 "register_operand")]
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UNSPEC_COND_FCVT))
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(set (match_operand:SVE_HSF 0 "register_operand")
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(unspec:SVE_HSF [(match_dup 4) (match_dup 5)] UNSPEC_UZP1))]
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"TARGET_SVE"
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@ -3862,10 +3865,9 @@
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[(set (match_operand:SVE_HSF 0 "register_operand" "=w")
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(unspec:SVE_HSF
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[(match_operand:<VWIDE_PRED> 1 "register_operand" "Upl")
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(unspec:SVE_HSF
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[(match_operand:<VWIDE> 2 "register_operand" "w")]
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UNSPEC_FLOAT_CONVERT)]
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UNSPEC_MERGE_PTRUE))]
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(match_operand:SI 3 "aarch64_sve_gp_strictness")
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(match_operand:<VWIDE> 2 "register_operand" "w")]
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UNSPEC_COND_FCVT))]
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"TARGET_SVE"
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"fcvt\t%0.<Vetype>, %1/m, %2.<Vewtype>"
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)
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@ -3896,8 +3898,9 @@
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: gen_aarch64_sve_zip1<mode>)
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(temp, operands[1], operands[1]));
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rtx ptrue = aarch64_ptrue_reg (<VWIDE_PRED>mode);
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emit_insn (gen_aarch64_sve_extend<mode><Vwide>2 (operands[0],
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ptrue, temp));
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rtx strictness = gen_int_mode (SVE_RELAXED_GP, SImode);
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emit_insn (gen_aarch64_sve_extend<mode><Vwide>2
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(operands[0], ptrue, temp, strictness));
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DONE;
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}
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)
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@ -3908,10 +3911,9 @@
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[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
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(unspec:<VWIDE>
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[(match_operand:<VWIDE_PRED> 1 "register_operand" "Upl")
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(unspec:<VWIDE>
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[(match_operand:SVE_HSF 2 "register_operand" "w")]
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UNSPEC_FLOAT_CONVERT)]
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UNSPEC_MERGE_PTRUE))]
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(match_operand:SI 3 "aarch64_sve_gp_strictness")
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(match_operand:SVE_HSF 2 "register_operand" "w")]
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UNSPEC_COND_FCVT))]
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"TARGET_SVE"
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"fcvt\t%0.<Vewtype>, %1/m, %2.<Vetype>"
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)
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@ -226,7 +226,6 @@
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UNSPEC_UNPACKSLO
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UNSPEC_UNPACKULO
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UNSPEC_PACK
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UNSPEC_FLOAT_CONVERT
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UNSPEC_WHILE_LO
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UNSPEC_LDN
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UNSPEC_STN
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@ -480,6 +480,9 @@
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UNSPEC_COND_FCMLT ; Used in aarch64-sve.md.
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UNSPEC_COND_FCMNE ; Used in aarch64-sve.md.
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UNSPEC_COND_FCMUO ; Used in aarch64-sve.md.
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UNSPEC_COND_FCVT ; Used in aarch64-sve.md.
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UNSPEC_COND_FCVTZS ; Used in aarch64-sve.md.
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UNSPEC_COND_FCVTZU ; Used in aarch64-sve.md.
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UNSPEC_COND_FDIV ; Used in aarch64-sve.md.
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UNSPEC_COND_FMAXNM ; Used in aarch64-sve.md.
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UNSPEC_COND_FMINNM ; Used in aarch64-sve.md.
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@ -498,6 +501,8 @@
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UNSPEC_COND_FRINTZ ; Used in aarch64-sve.md.
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UNSPEC_COND_FSQRT ; Used in aarch64-sve.md.
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UNSPEC_COND_FSUB ; Used in aarch64-sve.md.
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UNSPEC_COND_SCVTF ; Used in aarch64-sve.md.
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UNSPEC_COND_UCVTF ; Used in aarch64-sve.md.
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UNSPEC_LASTB ; Used in aarch64-sve.md.
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UNSPEC_FCADD90 ; Used in aarch64-simd.md.
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UNSPEC_FCADD270 ; Used in aarch64-simd.md.
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@ -1642,6 +1647,9 @@
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UNSPEC_COND_FRINTZ
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UNSPEC_COND_FSQRT])
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(define_int_iterator SVE_COND_FCVTI [UNSPEC_COND_FCVTZS UNSPEC_COND_FCVTZU])
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(define_int_iterator SVE_COND_ICVTF [UNSPEC_COND_SCVTF UNSPEC_COND_UCVTF])
|
||||
|
||||
(define_int_iterator SVE_COND_FP_BINARY [UNSPEC_COND_FADD
|
||||
UNSPEC_COND_FDIV
|
||||
UNSPEC_COND_FMAXNM
|
||||
@ -1715,6 +1723,9 @@
|
||||
(UNSPEC_FMINV "smin_nan")
|
||||
(UNSPEC_COND_FABS "abs")
|
||||
(UNSPEC_COND_FADD "add")
|
||||
(UNSPEC_COND_FCVT "fcvt")
|
||||
(UNSPEC_COND_FCVTZS "fix_trunc")
|
||||
(UNSPEC_COND_FCVTZU "fixuns_trunc")
|
||||
(UNSPEC_COND_FDIV "div")
|
||||
(UNSPEC_COND_FMAXNM "smax")
|
||||
(UNSPEC_COND_FMINNM "smin")
|
||||
@ -1732,7 +1743,9 @@
|
||||
(UNSPEC_COND_FRINTX "rint")
|
||||
(UNSPEC_COND_FRINTZ "btrunc")
|
||||
(UNSPEC_COND_FSQRT "sqrt")
|
||||
(UNSPEC_COND_FSUB "sub")])
|
||||
(UNSPEC_COND_FSUB "sub")
|
||||
(UNSPEC_COND_SCVTF "float")
|
||||
(UNSPEC_COND_UCVTF "floatuns")])
|
||||
|
||||
(define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax")
|
||||
(UNSPEC_UMINV "umin")
|
||||
@ -1773,7 +1786,11 @@
|
||||
(UNSPEC_UNPACKSLO "s")
|
||||
(UNSPEC_UNPACKULO "u")
|
||||
(UNSPEC_SMUL_HIGHPART "s")
|
||||
(UNSPEC_UMUL_HIGHPART "u")])
|
||||
(UNSPEC_UMUL_HIGHPART "u")
|
||||
(UNSPEC_COND_FCVTZS "s")
|
||||
(UNSPEC_COND_FCVTZU "u")
|
||||
(UNSPEC_COND_SCVTF "s")
|
||||
(UNSPEC_COND_UCVTF "u")])
|
||||
|
||||
(define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
|
||||
(UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
|
||||
|
||||
Loading…
Reference in New Issue
Block a user