[AArch64][5/5] Cleanup immediate generation code in aarch64_internal_mov_immediate
2015-09-20 Wilco Dijkstra <wdijkstr@arm.com> * config/aarch64/aarch64.c (aarch64_internal_mov_immediate): Cleanup immediate generation code. From-SVN: r227950
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@ -1,3 +1,8 @@
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2015-09-20 Wilco Dijkstra <wdijkstr@arm.com>
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* config/aarch64/aarch64.c (aarch64_internal_mov_immediate): Cleanup
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immediate generation code.
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2015-09-20 Wilco Dijkstra <wdijkstr@arm.com>
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* config/aarch64/aarch64.c (aarch64_internal_mov_immediate): Remove
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@ -1433,75 +1433,42 @@ static int
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aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
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machine_mode mode)
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{
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unsigned HOST_WIDE_INT mask;
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int i;
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bool first;
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unsigned HOST_WIDE_INT val, val2;
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int one_match, zero_match, first_not_ffff_match;
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int num_insns = 0;
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unsigned HOST_WIDE_INT val, val2, mask;
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int one_match, zero_match;
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int num_insns;
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if (CONST_INT_P (imm) && aarch64_move_imm (INTVAL (imm), mode))
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val = INTVAL (imm);
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if (aarch64_move_imm (val, mode))
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{
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if (generate)
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emit_insn (gen_rtx_SET (dest, imm));
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num_insns++;
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return num_insns;
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return 1;
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}
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if (mode == SImode)
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if ((val >> 32) == 0 || mode == SImode)
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{
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/* We know we can't do this in 1 insn, and we must be able to do it
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in two; so don't mess around looking for sequences that don't buy
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us anything. */
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if (generate)
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{
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emit_insn (gen_rtx_SET (dest, GEN_INT (INTVAL (imm) & 0xffff)));
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emit_insn (gen_insv_immsi (dest, GEN_INT (16),
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GEN_INT ((INTVAL (imm) >> 16) & 0xffff)));
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emit_insn (gen_rtx_SET (dest, GEN_INT (val & 0xffff)));
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if (mode == SImode)
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emit_insn (gen_insv_immsi (dest, GEN_INT (16),
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GEN_INT ((val >> 16) & 0xffff)));
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else
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emit_insn (gen_insv_immdi (dest, GEN_INT (16),
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GEN_INT ((val >> 16) & 0xffff)));
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}
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num_insns += 2;
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return num_insns;
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return 2;
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}
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/* Remaining cases are all for DImode. */
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val = INTVAL (imm);
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one_match = 0;
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zero_match = 0;
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mask = 0xffff;
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first_not_ffff_match = -1;
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for (i = 0; i < 64; i += 16, mask <<= 16)
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{
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if ((val & mask) == mask)
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one_match++;
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else
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{
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if (first_not_ffff_match < 0)
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first_not_ffff_match = i;
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if ((val & mask) == 0)
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zero_match++;
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}
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}
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if (one_match == 2)
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{
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/* Set one of the quarters and then insert back into result. */
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mask = 0xffffll << first_not_ffff_match;
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if (generate)
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{
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emit_insn (gen_rtx_SET (dest, GEN_INT (val | mask)));
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emit_insn (gen_insv_immdi (dest, GEN_INT (first_not_ffff_match),
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GEN_INT ((val >> first_not_ffff_match)
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& 0xffff)));
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}
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num_insns += 2;
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return num_insns;
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}
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if (zero_match == 2)
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goto simple_sequence;
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zero_match = ((val & mask) == 0) + ((val & (mask << 16)) == 0) +
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((val & (mask << 32)) == 0) + ((val & (mask << 48)) == 0);
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one_match = ((~val & mask) == 0) + ((~val & (mask << 16)) == 0) +
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((~val & (mask << 32)) == 0) + ((~val & (mask << 48)) == 0);
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if (zero_match != 2 && one_match != 2)
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{
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@ -1529,58 +1496,32 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
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{
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emit_insn (gen_rtx_SET (dest, GEN_INT (val2)));
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emit_insn (gen_insv_immdi (dest, GEN_INT (i),
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GEN_INT ((val >> i) & 0xffff)));
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GEN_INT ((val >> i) & 0xffff)));
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}
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return 2;
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}
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}
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if (one_match > zero_match)
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{
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/* Set either first three quarters or all but the third. */
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mask = 0xffffll << (16 - first_not_ffff_match);
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if (generate)
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emit_insn (gen_rtx_SET (dest,
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GEN_INT (val | mask | 0xffffffff00000000ull)));
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num_insns ++;
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/* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
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are emitted by the initial mov. If one_match > zero_match, skip set bits,
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otherwise skip zero bits. */
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/* Now insert other two quarters. */
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for (i = first_not_ffff_match + 16, mask <<= (first_not_ffff_match << 1);
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i < 64; i += 16, mask <<= 16)
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{
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if ((val & mask) != mask)
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{
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if (generate)
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emit_insn (gen_insv_immdi (dest, GEN_INT (i),
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GEN_INT ((val >> i) & 0xffff)));
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num_insns ++;
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}
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}
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return num_insns;
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}
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simple_sequence:
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first = true;
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num_insns = 1;
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mask = 0xffff;
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for (i = 0; i < 64; i += 16, mask <<= 16)
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val2 = one_match > zero_match ? ~val : val;
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i = (val2 & mask) != 0 ? 0 : (val2 & (mask << 16)) != 0 ? 16 : 32;
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if (generate)
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emit_insn (gen_rtx_SET (dest, GEN_INT (one_match > zero_match
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? (val | ~(mask << i))
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: (val & (mask << i)))));
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for (i += 16; i < 64; i += 16)
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{
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if ((val & mask) != 0)
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{
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if (first)
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{
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if (generate)
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emit_insn (gen_rtx_SET (dest, GEN_INT (val & mask)));
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num_insns ++;
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first = false;
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}
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else
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{
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if (generate)
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emit_insn (gen_insv_immdi (dest, GEN_INT (i),
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GEN_INT ((val >> i) & 0xffff)));
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num_insns ++;
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}
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}
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if ((val2 & (mask << i)) == 0)
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continue;
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if (generate)
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emit_insn (gen_insv_immdi (dest, GEN_INT (i),
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GEN_INT ((val >> i) & 0xffff)));
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num_insns ++;
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}
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return num_insns;
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