[AArch64][4/5] Remove redundant code
2015-09-20 Wilco Dijkstra <wdijkstr@arm.com> * config/aarch64/aarch64.c (aarch64_internal_mov_immediate): Remove redundant immediate generation code. From-SVN: r227949
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@ -1,3 +1,8 @@
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2015-09-20 Wilco Dijkstra <wdijkstr@arm.com>
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* config/aarch64/aarch64.c (aarch64_internal_mov_immediate): Remove
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redundant immediate generation code.
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2015-09-20 Wilco Dijkstra <wdijkstr@arm.com>
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* config/aarch64/aarch64.c (aarch64_bitmasks): Remove.
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@ -1437,8 +1437,6 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
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int i;
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bool first;
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unsigned HOST_WIDE_INT val, val2;
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bool subtargets;
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rtx subtarget;
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int one_match, zero_match, first_not_ffff_match;
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int num_insns = 0;
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@ -1468,7 +1466,6 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
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/* Remaining cases are all for DImode. */
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val = INTVAL (imm);
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subtargets = optimize && can_create_pseudo_p ();
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one_match = 0;
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zero_match = 0;
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@ -1506,63 +1503,6 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
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if (zero_match == 2)
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goto simple_sequence;
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mask = 0x0ffff0000UL;
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for (i = 16; i < 64; i += 16, mask <<= 16)
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{
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HOST_WIDE_INT comp = mask & ~(mask - 1);
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if (aarch64_uimm12_shift (val - (val & mask)))
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{
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if (generate)
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{
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subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
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emit_insn (gen_rtx_SET (subtarget, GEN_INT (val & mask)));
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emit_insn (gen_adddi3 (dest, subtarget,
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GEN_INT (val - (val & mask))));
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}
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num_insns += 2;
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return num_insns;
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}
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else if (aarch64_uimm12_shift (-(val - ((val + comp) & mask))))
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{
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if (generate)
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{
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subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
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emit_insn (gen_rtx_SET (subtarget,
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GEN_INT ((val + comp) & mask)));
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emit_insn (gen_adddi3 (dest, subtarget,
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GEN_INT (val - ((val + comp) & mask))));
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}
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num_insns += 2;
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return num_insns;
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}
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else if (aarch64_uimm12_shift (val - ((val - comp) | ~mask)))
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{
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if (generate)
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{
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subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
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emit_insn (gen_rtx_SET (subtarget,
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GEN_INT ((val - comp) | ~mask)));
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emit_insn (gen_adddi3 (dest, subtarget,
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GEN_INT (val - ((val - comp) | ~mask))));
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}
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num_insns += 2;
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return num_insns;
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}
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else if (aarch64_uimm12_shift (-(val - (val | ~mask))))
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{
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if (generate)
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{
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subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
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emit_insn (gen_rtx_SET (subtarget, GEN_INT (val | ~mask)));
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emit_insn (gen_adddi3 (dest, subtarget,
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GEN_INT (val - (val | ~mask))));
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}
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num_insns += 2;
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return num_insns;
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}
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}
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if (zero_match != 2 && one_match != 2)
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{
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/* Try emitting a bitmask immediate with a movk replacing 16 bits.
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