rs6000.md (strlensi): Don't use subsi3 with a constant, use addsi3 directly.
2014-09-21 Segher Boessenkool <segher@kernel.crashing.org> * config/rs6000/rs6000.md (strlensi): Don't use subsi3 with a constant, use addsi3 directly. (three anonymous define_insn, two define_split): Delete. (sub<mode>3): Move. Do not allow constant second operand. Generate different insn for constant first operand. (*subf<mode>3, *subf<mode>3_dot, *subf<mode>3_dot2): New. (subf<mode>3_imm): New. (ctz<mode>2, ffs<mode>2): Clobber CA_REGNO where required. (*plus_ltu<mode>): Only handle registers. (*plus_ltu<mode>_1): New. Handle integer third operand. (*plus_gtu<mode>): Only handle registers. (*plus_gtu<mode>_1): New. Handle integer third operand. From-SVN: r215434
This commit is contained in:
Segher Boessenkool
Segher Boessenkool
parent
b4e2da9e22
commit
9f31288f44
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@ -1,3 +1,18 @@
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2014-09-21 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/rs6000.md (strlensi): Don't use subsi3 with a
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constant, use addsi3 directly.
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(three anonymous define_insn, two define_split): Delete.
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(sub<mode>3): Move. Do not allow constant second operand.
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Generate different insn for constant first operand.
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(*subf<mode>3, *subf<mode>3_dot, *subf<mode>3_dot2): New.
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(subf<mode>3_imm): New.
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(ctz<mode>2, ffs<mode>2): Clobber CA_REGNO where required.
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(*plus_ltu<mode>): Only handle registers.
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(*plus_ltu<mode>_1): New. Handle integer third operand.
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(*plus_gtu<mode>): Only handle registers.
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(*plus_gtu<mode>_1): New. Handle integer third operand.
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2014-09-21 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/rs6000.md (iorxor): New code_iterator.
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@ -1427,7 +1427,7 @@
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emit_label (end_label);
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emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
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emit_insn (gen_subsi3 (result, scratch_string, addr));
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emit_insn (gen_subsi3 (result, result, const1_rtx));
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emit_insn (gen_addsi3 (result, result, constm1_rtx));
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DONE;
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})
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@ -1644,92 +1644,82 @@
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(set_attr "length" "4,8")])
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(define_insn ""
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
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(minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
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(match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
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""
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"@
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subf %0,%2,%1
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subfic %0,%2,%1"
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[(set_attr "type" "add")])
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(define_insn ""
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
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(compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
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(match_operand:P 2 "gpc_reg_operand" "r,r"))
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(const_int 0)))
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(clobber (match_scratch:P 3 "=r,r"))]
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""
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"@
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subf. %3,%2,%1
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#"
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[(set_attr "type" "add")
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(set_attr "dot" "yes")
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(set_attr "length" "4,8")])
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(define_split
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[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
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(compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
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(match_operand:P 2 "gpc_reg_operand" ""))
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(const_int 0)))
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(clobber (match_scratch:P 3 ""))]
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"reload_completed"
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[(set (match_dup 3)
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(minus:P (match_dup 1)
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(match_dup 2)))
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(set (match_dup 0)
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(compare:CC (match_dup 3)
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(const_int 0)))]
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"")
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(define_insn ""
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
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(compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
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(match_operand:P 2 "gpc_reg_operand" "r,r"))
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(const_int 0)))
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(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
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(minus:P (match_dup 1)
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(match_dup 2)))]
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""
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"@
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subf. %0,%2,%1
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#"
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[(set_attr "type" "add")
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(set_attr "dot" "yes")
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(set_attr "length" "4,8")])
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(define_split
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[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
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(compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
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(match_operand:P 2 "gpc_reg_operand" ""))
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(const_int 0)))
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(set (match_operand:P 0 "gpc_reg_operand" "")
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(minus:P (match_dup 1)
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(match_dup 2)))]
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"reload_completed"
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[(set (match_dup 0)
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(minus:P (match_dup 1)
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(match_dup 2)))
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(set (match_dup 3)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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"")
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(define_expand "sub<mode>3"
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[(set (match_operand:SDI 0 "gpc_reg_operand" "")
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(minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
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(match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
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(match_operand:SDI 2 "gpc_reg_operand" "")))]
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""
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"
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{
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if (GET_CODE (operands[2]) == CONST_INT)
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if (short_cint_operand (operands[1], <MODE>mode)
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&& !(<MODE>mode == DImode && !TARGET_POWERPC64))
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{
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emit_insn (gen_add<mode>3 (operands[0], operands[1],
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negate_rtx (<MODE>mode, operands[2])));
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emit_insn (gen_subf<mode>3_imm (operands[0], operands[2], operands[1]));
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DONE;
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}
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}")
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})
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(define_insn "*subf<mode>3"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
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(minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r")
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(match_operand:GPR 1 "gpc_reg_operand" "r")))]
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""
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"subf %0,%1,%2"
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[(set_attr "type" "add")])
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(define_insn_and_split "*subf<mode>3_dot"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
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(compare:CC (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r")
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(match_operand:GPR 1 "gpc_reg_operand" "r,r"))
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(const_int 0)))
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(clobber (match_scratch:GPR 0 "=r,r"))]
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"<MODE>mode == Pmode"
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"@
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subf. %0,%1,%2
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#"
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"&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
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[(set (match_dup 0)
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(minus:GPR (match_dup 2)
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(match_dup 1)))
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(set (match_dup 3)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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""
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[(set_attr "type" "add")
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(set_attr "dot" "yes")
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(set_attr "length" "4,8")])
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(define_insn_and_split "*subf<mode>3_dot2"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
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(compare:CC (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r")
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(match_operand:GPR 1 "gpc_reg_operand" "r,r"))
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(const_int 0)))
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(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
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(minus:GPR (match_dup 2)
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(match_dup 1)))]
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"<MODE>mode == Pmode"
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"@
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subf. %0,%1,%2
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#"
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"&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
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[(set (match_dup 0)
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(minus:GPR (match_dup 2)
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(match_dup 1)))
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(set (match_dup 3)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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""
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[(set_attr "type" "add")
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(set_attr "dot" "yes")
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(set_attr "length" "4,8")])
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(define_insn "subf<mode>3_imm"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
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(minus:GPR (match_operand:GPR 2 "short_cint_operand" "I")
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(match_operand:GPR 1 "gpc_reg_operand" "r")))
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(clobber (reg:GPR CA_REGNO))]
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""
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"subfic %0,%1,%2"
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[(set_attr "type" "add")])
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(define_expand "neg<mode>2"
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@ -1802,9 +1792,10 @@
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(match_dup 2)))
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(set (match_dup 4)
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(clz:GPR (match_dup 3)))
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(set (match_operand:GPR 0 "gpc_reg_operand" "")
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(minus:GPR (match_dup 5)
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(match_dup 4)))]
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(parallel [(set (match_operand:GPR 0 "gpc_reg_operand" "")
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(minus:GPR (match_dup 5)
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(match_dup 4)))
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(clobber (reg:GPR CA_REGNO))])]
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""
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{
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operands[2] = gen_reg_rtx (<MODE>mode);
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@ -1821,9 +1812,10 @@
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(match_dup 2)))
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(set (match_dup 4)
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(clz:GPR (match_dup 3)))
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(set (match_operand:GPR 0 "gpc_reg_operand" "")
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(minus:GPR (match_dup 5)
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(match_dup 4)))]
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(parallel [(set (match_operand:GPR 0 "gpc_reg_operand" "")
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(minus:GPR (match_dup 5)
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(match_dup 4)))
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(clobber (reg:GPR CA_REGNO))])]
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""
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{
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operands[2] = gen_reg_rtx (<MODE>mode);
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@ -12582,7 +12574,7 @@
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[(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
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(plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
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(match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
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(match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
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(match_operand:P 3 "gpc_reg_operand" "r,r")))]
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""
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"#"
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"&& !reg_overlap_mentioned_p (operands[0], operands[3])"
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@ -12590,6 +12582,19 @@
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(set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
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"")
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(define_insn_and_split "*plus_ltu<mode>_1"
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[(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
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(plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
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(match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
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(match_operand:P 3 "short_cint_operand" "I,I")))]
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""
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"#"
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"&& !reg_overlap_mentioned_p (operands[0], operands[3])"
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[(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
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(parallel [(set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))
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(clobber (reg:P CA_REGNO))])]
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"")
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(define_insn_and_split "*plus_ltu<mode>_compare"
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[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
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(compare:CC
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@ -13014,7 +13019,7 @@
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[(set (match_operand:P 0 "gpc_reg_operand" "=&r")
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(plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
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(match_operand:P 2 "reg_or_short_operand" "rI"))
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(match_operand:P 3 "reg_or_short_operand" "rI")))]
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(match_operand:P 3 "gpc_reg_operand" "r")))]
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""
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"#"
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"&& !reg_overlap_mentioned_p (operands[0], operands[3])"
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@ -13022,6 +13027,19 @@
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(set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
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"")
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(define_insn_and_split "*plus_gtu<mode>_1"
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[(set (match_operand:P 0 "gpc_reg_operand" "=&r")
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(plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
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(match_operand:P 2 "reg_or_short_operand" "rI"))
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(match_operand:P 3 "short_cint_operand" "I")))]
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""
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"#"
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"&& !reg_overlap_mentioned_p (operands[0], operands[3])"
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[(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
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(parallel [(set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))
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(clobber (reg:P CA_REGNO))])]
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"")
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(define_insn_and_split "*plus_gtu<mode>_compare"
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[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
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(compare:CC
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