rs6000: Make all rlw*nm and rld*c* type shift
They are often labeled just "integer" currently. Fix that. Also handle shift properly in those scheduling descriptions that neglected it. From-SVN: r210873
This commit is contained in:
Segher Boessenkool
Segher Boessenkool
parent
73c076c8a2
commit
a35dd1fae7
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@ -1,3 +1,32 @@
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2014-05-23 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/440.md (ppc440-integer): Include shift without
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dot.
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(ppc440-compare): Include shift with dot.
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* config/rs6000/e300c2c3.md (ppce300c3_iu): Include shift without
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dot.
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* config/rs6000/e5500.md (e5500_sfx2): Include constant shift
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without dot.
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* config/rs6000/e6500.md (e6500_sfx): Exclude constant shift
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without dot.
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(e6500_sfx2): Include it.
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* config/rs6000/rs6000.md ( *zero_extend<mode>di2_internal1,
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*zero_extend<mode>di2_internal2, *zero_extend<mode>di2_internal3,
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*zero_extendsidi2_lfiwzx, andsi3_mc, andsi3_nomc,
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andsi3_internal0_nomc, extzvsi_internal, extzvdi_internal,
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*extzvdi_internal1, *extzvdi_internal2, rotlsi3, *rotlsi3_64,
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*rotlsi3_internal4, *rotlsi3_internal7le, *rotlsi3_internal7be,
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*rotlsi3_internal10le, *rotlsi3_internal10be, rlwinm,
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*lshiftrt_internal1le, *lshiftrt_internal1be,
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*lshiftrt_internal4le, *lshiftrt_internal4be, rotldi3,
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*rotldi3_internal4, *rotldi3_internal7le, *rotldi3_internal7be,
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*rotldi3_internal10le, *rotldi3_internal10be,
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*rotldi3_internal13le, *rotldi3_internal13be, *ashldi3_internal4,
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ashldi3_internal5, *ashldi3_internal6, *ashldi3_internal7,
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ashldi3_internal8, *ashldi3_internal9, anddi3_mc, anddi3_nomc,
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*anddi3_internal2_mc, *anddi3_internal3_mc, and 4 anonymous
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define_insns): Use type "shift" in the appropriate alternatives.
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2014-05-23 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/rs6000.md (type): Add "logical". Delete
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@ -53,8 +53,8 @@
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"ppc440_issue,ppc440_l_pipe")
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(define_insn_reservation "ppc440-integer" 1
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(and (ior (eq_attr "type" "integer,insert,shift,trap,cntlz,exts,isel")
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(and (eq_attr "type" "add,logical")
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(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
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(and (eq_attr "type" "add,logical,shift")
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(eq_attr "dot" "no")))
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(eq_attr "cpu" "ppc440"))
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"ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")
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@ -96,7 +96,7 @@
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(define_insn_reservation "ppc440-compare" 2
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(and (ior (eq_attr "type" "cmp,compare,cr_logical,delayed_cr,mfcr")
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(and (eq_attr "type" "add,logical")
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(and (eq_attr "type" "add,logical,shift")
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(eq_attr "dot" "yes")))
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(eq_attr "cpu" "ppc440"))
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"ppc440_issue,ppc440_i_pipe")
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@ -93,7 +93,7 @@
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;; Other one cycle IU insns
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(define_insn_reservation "ppce300c3_iu" 1
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(and (ior (eq_attr "type" "integer,insert,isel")
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(and (eq_attr "type" "add,logical")
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(and (eq_attr "type" "add,logical,shift")
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(eq_attr "dot" "no")))
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(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire")
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@ -67,7 +67,10 @@
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(define_insn_reservation "e5500_sfx2" 2
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(and (ior (eq_attr "type" "cmp,compare,trap")
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(and (eq_attr "type" "add,logical")
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(eq_attr "dot" "yes")))
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(eq_attr "dot" "yes"))
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(and (eq_attr "type" "shift")
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(eq_attr "dot" "yes")
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(eq_attr "var_shift" "no")))
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(eq_attr "cpu" "ppce5500"))
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"e5500_decode,e5500_sfx")
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@ -63,6 +63,7 @@
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(and (eq_attr "type" "add,logical")
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(eq_attr "dot" "no"))
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(and (eq_attr "type" "shift")
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(eq_attr "dot" "no")
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(eq_attr "var_shift" "no")))
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_sfx")
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@ -70,7 +71,10 @@
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(define_insn_reservation "e6500_sfx2" 2
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(and (ior (eq_attr "type" "cmp,compare,trap")
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(and (eq_attr "type" "add,logical")
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(eq_attr "dot" "yes")))
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(eq_attr "dot" "yes"))
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(and (eq_attr "type" "shift")
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(eq_attr "dot" "yes")
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(eq_attr "var_shift" "no")))
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(eq_attr "cpu" "ppce6500"))
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"e6500_decode,e6500_sfx")
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@ -565,7 +565,7 @@
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"@
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l<wd>z%U1%X1 %0,%1
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rldicl %0,%1,0,<dbits>"
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[(set_attr "type" "load,*")])
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[(set_attr "type" "load,shift")])
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(define_insn "*zero_extend<mode>di2_internal2"
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
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@ -576,7 +576,8 @@
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"@
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rldicl. %2,%1,0,<dbits>
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#"
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[(set_attr "type" "compare")
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[(set_attr "type" "shift")
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(set_attr "dot" "yes")
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(set_attr "length" "4,8")])
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(define_split
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@ -602,7 +603,8 @@
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"@
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rldicl. %0,%1,0,<dbits>
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#"
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[(set_attr "type" "compare")
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[(set_attr "type" "shift")
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(set_attr "dot" "yes")
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(set_attr "length" "4,8")])
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(define_split
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@ -629,7 +631,7 @@
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mtvsrwz %x0,%1
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lfiwzx %0,%y1
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lxsiwzx %x0,%y1"
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[(set_attr "type" "load,*,mffgpr,fpload,fpload")])
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[(set_attr "type" "load,shift,mffgpr,fpload,fpload")])
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(define_insn "extendqidi2"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
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@ -866,7 +868,7 @@
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"@
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lbz%U1%X1 %0,%1
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rlwinm %0,%1,0,0xff"
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[(set_attr "type" "load,*")])
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[(set_attr "type" "load,shift")])
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(define_insn ""
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
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@ -988,7 +990,7 @@
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"@
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lbz%U1%X1 %0,%1
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rlwinm %0,%1,0,0xff"
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[(set_attr "type" "load,*")])
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[(set_attr "type" "load,shift")])
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(define_insn ""
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
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@ -1116,7 +1118,7 @@
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"@
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lhz%U1%X1 %0,%1
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rlwinm %0,%1,0,0xffff"
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[(set_attr "type" "load,*")])
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[(set_attr "type" "load,shift")])
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(define_insn ""
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
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@ -2915,7 +2917,7 @@
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rlwinm %0,%1,0,%m2,%M2
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andi. %0,%1,%b2
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andis. %0,%1,%u2"
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[(set_attr "type" "*,*,logical,logical")
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[(set_attr "type" "*,shift,logical,logical")
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(set_attr "dot" "no,no,yes,yes")])
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(define_insn "andsi3_nomc"
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@ -2926,7 +2928,8 @@
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"!rs6000_gen_cell_microcode"
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"@
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and %0,%1,%2
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rlwinm %0,%1,0,%m2,%M2")
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rlwinm %0,%1,0,%m2,%M2"
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[(set_attr "type" "logical,shift")])
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(define_insn "andsi3_internal0_nomc"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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@ -2935,7 +2938,8 @@
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"!rs6000_gen_cell_microcode"
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"@
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and %0,%1,%2
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rlwinm %0,%1,0,%m2,%M2")
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rlwinm %0,%1,0,%m2,%M2"
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[(set_attr "type" "logical,shift")])
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;; Note to set cr's other than cr0 we do the and immediate and then
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@ -3665,7 +3669,8 @@
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else
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operands[3] = GEN_INT (start + size);
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return \"rlwinm %0,%1,%3,%s2,31\";
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}")
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}"
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[(set_attr "type" "shift")])
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(define_insn "*extzvsi_internal1"
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
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@ -3795,7 +3800,8 @@
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operands[3] = GEN_INT (start + size);
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operands[2] = GEN_INT (64 - size);
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return \"rldicl %0,%1,%3,%2\";
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}")
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}"
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[(set_attr "type" "shift")])
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(define_insn "*extzvdi_internal1"
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[(set (match_operand:CC 0 "gpc_reg_operand" "=x")
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@ -3817,7 +3823,8 @@
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operands[2] = GEN_INT (64 - size);
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return \"rldicl. %4,%1,%3,%2\";
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}"
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[(set_attr "type" "compare")])
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[(set_attr "type" "shift")
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(set_attr "dot" "yes")])
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(define_insn "*extzvdi_internal2"
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[(set (match_operand:CC 4 "gpc_reg_operand" "=x")
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@ -3840,7 +3847,8 @@
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operands[2] = GEN_INT (64 - size);
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return \"rldicl. %0,%1,%3,%2\";
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}"
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[(set_attr "type" "compare")])
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[(set_attr "type" "shift")
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(set_attr "dot" "yes")])
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(define_insn "rotlsi3"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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@ -3850,7 +3858,7 @@
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"@
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rlwnm %0,%1,%2,0xffffffff
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rlwinm %0,%1,%h2,0xffffffff"
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[(set_attr "type" "shift,integer")
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[(set_attr "type" "shift")
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(set_attr "var_shift" "yes,no")])
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(define_insn "*rotlsi3_64"
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@ -3862,7 +3870,7 @@
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"@
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rlwnm %0,%1,%2,0xffffffff
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rlwinm %0,%1,%h2,0xffffffff"
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[(set_attr "type" "shift,integer")
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[(set_attr "type" "shift")
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(set_attr "var_shift" "yes,no")])
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(define_insn "*rotlsi3_internal2"
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@ -3938,7 +3946,7 @@
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"@
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rlwnm %0,%1,%2,%m3,%M3
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rlwinm %0,%1,%h2,%m3,%M3"
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[(set_attr "type" "shift,integer")
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[(set_attr "type" "shift")
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(set_attr "var_shift" "yes,no")])
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(define_insn "*rotlsi3_internal5"
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@ -4026,7 +4034,8 @@
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[(set (attr "cell_micro")
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(if_then_else (match_operand:SI 2 "const_int_operand" "")
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(const_string "not")
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(const_string "always")))])
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(const_string "always")))
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(set_attr "type" "shift")])
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(define_insn "*rotlsi3_internal7be"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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@ -4039,7 +4048,8 @@
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[(set (attr "cell_micro")
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(if_then_else (match_operand:SI 2 "const_int_operand" "")
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(const_string "not")
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(const_string "always")))])
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(const_string "always")))
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(set_attr "type" "shift")])
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(define_insn "*rotlsi3_internal8le"
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
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@ -4199,7 +4209,7 @@
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"@
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rlwnm %0,%1,%2,0xffff
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rlwinm %0,%1,%h2,0xffff"
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[(set_attr "type" "shift,integer")
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[(set_attr "type" "shift")
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(set_attr "var_shift" "yes,no")])
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(define_insn "*rotlsi3_internal10be"
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@ -4212,7 +4222,7 @@
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"@
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rlwnm %0,%1,%2,0xffff
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rlwinm %0,%1,%h2,0xffff"
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[(set_attr "type" "shift,integer")
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[(set_attr "type" "shift")
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(set_attr "var_shift" "yes,no")])
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(define_insn "*rotlsi3_internal11le"
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@ -4456,7 +4466,8 @@
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(match_operand:SI 2 "const_int_operand" "i"))
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(match_operand:SI 3 "mask_operand" "n")))]
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"includes_lshift_p (operands[2], operands[3])"
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"rlwinm %0,%1,%h2,%m3,%M3")
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"rlwinm %0,%1,%h2,%m3,%M3"
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[(set_attr "type" "shift")])
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(define_insn ""
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
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@ -4623,7 +4634,8 @@
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(match_operand:SI 2 "const_int_operand" "i"))
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(match_operand:SI 3 "mask_operand" "n")))]
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"includes_rshift_p (operands[2], operands[3])"
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"rlwinm %0,%1,%s2,%m3,%M3")
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"rlwinm %0,%1,%s2,%m3,%M3"
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[(set_attr "type" "shift")])
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(define_insn ""
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
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@ -4699,7 +4711,8 @@
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(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
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(match_operand:SI 2 "const_int_operand" "i")) 0)))]
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"!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
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"rlwinm %0,%1,%s2,0xff")
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"rlwinm %0,%1,%s2,0xff"
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[(set_attr "type" "shift")])
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(define_insn "*lshiftrt_internal1be"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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@ -4708,7 +4721,8 @@
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(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
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(match_operand:SI 2 "const_int_operand" "i")) 3)))]
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"BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
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"rlwinm %0,%1,%s2,0xff")
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"rlwinm %0,%1,%s2,0xff"
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[(set_attr "type" "shift")])
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(define_insn "*lshiftrt_internal2le"
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
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@ -4861,7 +4875,8 @@
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(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
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(match_operand:SI 2 "const_int_operand" "i")) 0)))]
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"!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
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"rlwinm %0,%1,%s2,0xffff")
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"rlwinm %0,%1,%s2,0xffff"
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[(set_attr "type" "shift")])
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(define_insn "*lshiftrt_internal4be"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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@ -4870,7 +4885,8 @@
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(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
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(match_operand:SI 2 "const_int_operand" "i")) 2)))]
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"BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
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"rlwinm %0,%1,%s2,0xffff")
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"rlwinm %0,%1,%s2,0xffff"
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[(set_attr "type" "shift")])
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(define_insn "*lshiftrt_internal5le"
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
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@ -6969,7 +6985,7 @@
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"@
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rldcl %0,%1,%2,0
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rldicl %0,%1,%H2,0"
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[(set_attr "type" "shift,integer")
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[(set_attr "type" "shift")
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||||
(set_attr "var_shift" "yes,no")])
|
||||
|
||||
(define_insn "*rotldi3_internal2"
|
||||
|
|
@ -7045,7 +7061,7 @@
|
|||
"@
|
||||
rldc%B3 %0,%1,%2,%S3
|
||||
rldic%B3 %0,%1,%H2,%S3"
|
||||
[(set_attr "type" "shift,integer")
|
||||
[(set_attr "type" "shift")
|
||||
(set_attr "var_shift" "yes,no")])
|
||||
|
||||
(define_insn "*rotldi3_internal5"
|
||||
|
|
@ -7132,7 +7148,7 @@
|
|||
"@
|
||||
rldcl %0,%1,%2,56
|
||||
rldicl %0,%1,%H2,56"
|
||||
[(set_attr "type" "shift,integer")
|
||||
[(set_attr "type" "shift")
|
||||
(set_attr "var_shift" "yes,no")])
|
||||
|
||||
(define_insn "*rotldi3_internal7be"
|
||||
|
|
@ -7145,7 +7161,7 @@
|
|||
"@
|
||||
rldcl %0,%1,%2,56
|
||||
rldicl %0,%1,%H2,56"
|
||||
[(set_attr "type" "shift,integer")
|
||||
[(set_attr "type" "shift")
|
||||
(set_attr "var_shift" "yes,no")])
|
||||
|
||||
(define_insn "*rotldi3_internal8le"
|
||||
|
|
@ -7306,7 +7322,7 @@
|
|||
"@
|
||||
rldcl %0,%1,%2,48
|
||||
rldicl %0,%1,%H2,48"
|
||||
[(set_attr "type" "shift,integer")
|
||||
[(set_attr "type" "shift")
|
||||
(set_attr "var_shift" "yes,no")])
|
||||
|
||||
(define_insn "*rotldi3_internal10be"
|
||||
|
|
@ -7319,7 +7335,7 @@
|
|||
"@
|
||||
rldcl %0,%1,%2,48
|
||||
rldicl %0,%1,%H2,48"
|
||||
[(set_attr "type" "shift,integer")
|
||||
[(set_attr "type" "shift")
|
||||
(set_attr "var_shift" "yes,no")])
|
||||
|
||||
(define_insn "*rotldi3_internal11le"
|
||||
|
|
@ -7480,7 +7496,7 @@
|
|||
"@
|
||||
rldcl %0,%1,%2,32
|
||||
rldicl %0,%1,%H2,32"
|
||||
[(set_attr "type" "shift,integer")
|
||||
[(set_attr "type" "shift")
|
||||
(set_attr "var_shift" "yes,no")])
|
||||
|
||||
(define_insn "*rotldi3_internal13be"
|
||||
|
|
@ -7493,7 +7509,7 @@
|
|||
"@
|
||||
rldcl %0,%1,%2,32
|
||||
rldicl %0,%1,%H2,32"
|
||||
[(set_attr "type" "shift,integer")
|
||||
[(set_attr "type" "shift")
|
||||
(set_attr "var_shift" "yes,no")])
|
||||
|
||||
(define_insn "*rotldi3_internal14le"
|
||||
|
|
@ -7732,7 +7748,8 @@
|
|||
(match_operand:SI 2 "const_int_operand" "i"))
|
||||
(match_operand:DI 3 "const_int_operand" "n")))]
|
||||
"TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
|
||||
"rldic %0,%1,%H2,%W3")
|
||||
"rldic %0,%1,%H2,%W3"
|
||||
[(set_attr "type" "shift")])
|
||||
|
||||
(define_insn "ashldi3_internal5"
|
||||
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
|
||||
|
|
@ -7746,7 +7763,8 @@
|
|||
"@
|
||||
rldic. %4,%1,%H2,%W3
|
||||
#"
|
||||
[(set_attr "type" "compare")
|
||||
[(set_attr "type" "shift")
|
||||
(set_attr "dot" "yes")
|
||||
(set_attr "length" "4,8")])
|
||||
|
||||
(define_split
|
||||
|
|
@ -7780,7 +7798,8 @@
|
|||
"@
|
||||
rldic. %0,%1,%H2,%W3
|
||||
#"
|
||||
[(set_attr "type" "compare")
|
||||
[(set_attr "type" "shift")
|
||||
(set_attr "dot" "yes")
|
||||
(set_attr "length" "4,8")])
|
||||
|
||||
(define_split
|
||||
|
|
@ -7808,7 +7827,8 @@
|
|||
(match_operand:SI 2 "const_int_operand" "i"))
|
||||
(match_operand:DI 3 "mask64_operand" "n")))]
|
||||
"TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
|
||||
"rldicr %0,%1,%H2,%S3")
|
||||
"rldicr %0,%1,%H2,%S3"
|
||||
[(set_attr "type" "shift")])
|
||||
|
||||
(define_insn "ashldi3_internal8"
|
||||
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
|
||||
|
|
@ -7822,7 +7842,8 @@
|
|||
"@
|
||||
rldicr. %4,%1,%H2,%S3
|
||||
#"
|
||||
[(set_attr "type" "compare")
|
||||
[(set_attr "type" "shift")
|
||||
(set_attr "dot" "yes")
|
||||
(set_attr "length" "4,8")])
|
||||
|
||||
(define_split
|
||||
|
|
@ -7856,7 +7877,8 @@
|
|||
"@
|
||||
rldicr. %0,%1,%H2,%S3
|
||||
#"
|
||||
[(set_attr "type" "compare")
|
||||
[(set_attr "type" "shift")
|
||||
(set_attr "dot" "yes")
|
||||
(set_attr "length" "4,8")])
|
||||
|
||||
(define_split
|
||||
|
|
@ -8084,7 +8106,7 @@
|
|||
andi. %0,%1,%b2
|
||||
andis. %0,%1,%u2
|
||||
#"
|
||||
[(set_attr "type" "*,*,*,logical,logical,*")
|
||||
[(set_attr "type" "*,shift,shift,logical,logical,*")
|
||||
(set_attr "dot" "no,no,no,yes,yes,no")
|
||||
(set_attr "length" "4,4,4,4,4,8")])
|
||||
|
||||
|
|
@ -8099,7 +8121,8 @@
|
|||
rldic%B2 %0,%1,0,%S2
|
||||
rlwinm %0,%1,0,%m2,%M2
|
||||
#"
|
||||
[(set_attr "length" "4,4,4,8")])
|
||||
[(set_attr "type" "*,shift,shift,*")
|
||||
(set_attr "length" "4,4,4,8")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:DI 0 "gpc_reg_operand" "")
|
||||
|
|
@ -8143,7 +8166,7 @@
|
|||
#
|
||||
#
|
||||
#"
|
||||
[(set_attr "type" "logical,compare,shift,logical,\
|
||||
[(set_attr "type" "logical,shift,shift,logical,\
|
||||
logical,compare,compare,compare,compare,compare,\
|
||||
compare,compare")
|
||||
(set_attr "dot" "yes")
|
||||
|
|
@ -8197,7 +8220,7 @@
|
|||
#
|
||||
#
|
||||
#"
|
||||
[(set_attr "type" "logical,compare,shift,logical,\
|
||||
[(set_attr "type" "logical,shift,shift,logical,\
|
||||
logical,compare,compare,compare,compare,compare,\
|
||||
compare,compare")
|
||||
(set_attr "dot" "yes")
|
||||
|
|
|
|||
Loading…
Reference in New Issue