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Fix ChangeLog formatting. 

gcc/
Fix ChangeLog formatting.

gcc/testsuite
2013-03-25  Kyrylo Tkachov  <kyrylo.tkachov at arm.com>

	* gcc.target/aarch64/atomic-comp-swap-release-acquire.c: Move test
	body from here...
	* gcc.target/aarch64/atomic-comp-swap-release-acquire.x: ... to here.
	* gcc.target/aarch64/atomic-op-acq_rel.c: Move test body from here...
	* gcc.target/aarch64/atomic-op-acq_rel.x: ... to here.
	* gcc.target/aarch64/atomic-op-acquire.c: Move test body from here...
	* gcc.target/aarch64/atomic-op-acquire.x: ... to here.
	* gcc.target/aarch64/atomic-op-char.c: Move test body from here...
	* gcc.target/aarch64/atomic-op-char.x: ... to here.
	* gcc.target/aarch64/atomic-op-consume.c: Move test body from here...
	* gcc.target/aarch64/atomic-op-consume.x: ... to here.
	* gcc.target/aarch64/atomic-op-int.c: Move test body from here...
	* gcc.target/aarch64/atomic-op-int.x: ... to here.
	* gcc.target/aarch64/atomic-op-relaxed.c: Move test body from here...
	* gcc.target/aarch64/atomic-op-relaxed.x: ... to here.
	* gcc.target/aarch64/atomic-op-release.c: Move test body from here...
	* gcc.target/aarch64/atomic-op-release.x: ... to here.
	* gcc.target/aarch64/atomic-op-seq_cst.c: Move test body from here...
	* gcc.target/aarch64/atomic-op-seq_cst.x: ... to here.
	* gcc.target/aarch64/atomic-op-short.c: Move test body from here...
	* gcc.target/aarch64/atomic-op-short.x: ... to here.
	* gcc.target/arm/atomic-comp-swap-release-acquire.c: New test.
	* gcc.target/arm/atomic-op-acq_rel.c: Likewise.
	* gcc.target/arm/atomic-op-acquire.c: Likewise.
	* gcc.target/arm/atomic-op-char.c: Likewise.
	* gcc.target/arm/atomic-op-consume.c: Likewise.
	* gcc.target/arm/atomic-op-int.c: Likewise.
	* gcc.target/arm/atomic-op-relaxed.c: Likewise.
	* gcc.target/arm/atomic-op-release.c: Likewise.
	* gcc.target/arm/atomic-op-seq_cst.c: Likewise.
	* gcc.target/arm/atomic-op-short.c: Likewise.

From-SVN: r197051
This commit is contained in:
Kyrylo Tkachov 2013-03-25 14:55:05 +00:00 committed by Kyrylo Tkachov
parent 55446c7e55
commit a5784ce624
32 changed files with 514 additions and 368 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
gcc/ChangeLog
View File

@ -70,6 +70,7 @@
for microMIPS.add<mode>3"
2013-03-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/56720
* config/arm/iterators.md (v_cmp_result): New mode attribute.
* config/arm/neon.md (vcond<mode><mode>): Handle unordered cases.

34
gcc/testsuite/ChangeLog
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@ -1,3 +1,37 @@
2013-03-25 Kyrylo Tkachov <kyrylo.tkachov at arm.com>
* gcc.target/aarch64/atomic-comp-swap-release-acquire.c: Move test
body from here...
* gcc.target/aarch64/atomic-comp-swap-release-acquire.x: ... to here.
* gcc.target/aarch64/atomic-op-acq_rel.c: Move test body from here...
* gcc.target/aarch64/atomic-op-acq_rel.x: ... to here.
* gcc.target/aarch64/atomic-op-acquire.c: Move test body from here...
* gcc.target/aarch64/atomic-op-acquire.x: ... to here.
* gcc.target/aarch64/atomic-op-char.c: Move test body from here...
* gcc.target/aarch64/atomic-op-char.x: ... to here.
* gcc.target/aarch64/atomic-op-consume.c: Move test body from here...
* gcc.target/aarch64/atomic-op-consume.x: ... to here.
* gcc.target/aarch64/atomic-op-int.c: Move test body from here...
* gcc.target/aarch64/atomic-op-int.x: ... to here.
* gcc.target/aarch64/atomic-op-relaxed.c: Move test body from here...
* gcc.target/aarch64/atomic-op-relaxed.x: ... to here.
* gcc.target/aarch64/atomic-op-release.c: Move test body from here...
* gcc.target/aarch64/atomic-op-release.x: ... to here.
* gcc.target/aarch64/atomic-op-seq_cst.c: Move test body from here...
* gcc.target/aarch64/atomic-op-seq_cst.x: ... to here.
* gcc.target/aarch64/atomic-op-short.c: Move test body from here...
* gcc.target/aarch64/atomic-op-short.x: ... to here.
* gcc.target/arm/atomic-comp-swap-release-acquire.c: New test.
* gcc.target/arm/atomic-op-acq_rel.c: Likewise.
* gcc.target/arm/atomic-op-acquire.c: Likewise.
* gcc.target/arm/atomic-op-char.c: Likewise.
* gcc.target/arm/atomic-op-consume.c: Likewise.
* gcc.target/arm/atomic-op-int.c: Likewise.
* gcc.target/arm/atomic-op-relaxed.c: Likewise.
* gcc.target/arm/atomic-op-release.c: Likewise.
* gcc.target/arm/atomic-op-seq_cst.c: Likewise.
* gcc.target/arm/atomic-op-short.c: Likewise.
2013-03-25 Richard Biener <rguenther@suse.de>
PR middle-end/56694

36
gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c
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@ -1,41 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
#define STRONG 0
#define WEAK 1
int v = 0;
int
atomic_compare_exchange_STRONG_RELEASE_ACQUIRE (int a, int b)
{
return __atomic_compare_exchange (&v, &a, &b,
STRONG, __ATOMIC_RELEASE,
__ATOMIC_ACQUIRE);
}
int
atomic_compare_exchange_WEAK_RELEASE_ACQUIRE (int a, int b)
{
return __atomic_compare_exchange (&v, &a, &b,
WEAK, __ATOMIC_RELEASE,
__ATOMIC_ACQUIRE);
}
int
atomic_compare_exchange_n_STRONG_RELEASE_ACQUIRE (int a, int b)
{
return __atomic_compare_exchange_n (&v, &a, b,
STRONG, __ATOMIC_RELEASE,
__ATOMIC_ACQUIRE);
}
int
atomic_compare_exchange_n_WEAK_RELEASE_ACQUIRE (int a, int b)
{
return __atomic_compare_exchange_n (&v, &a, b,
WEAK, __ATOMIC_RELEASE,
__ATOMIC_ACQUIRE);
}
#include "atomic-comp-swap-release-acquire.x"
/* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 4 } } */
/* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 4 } } */

36
gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.x Normal file
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@ -0,0 +1,36 @@
#define STRONG 0
#define WEAK 1
int v = 0;
int
atomic_compare_exchange_STRONG_RELEASE_ACQUIRE (int a, int b)
{
return __atomic_compare_exchange (&v, &a, &b,
STRONG, __ATOMIC_RELEASE,
__ATOMIC_ACQUIRE);
}
int
atomic_compare_exchange_WEAK_RELEASE_ACQUIRE (int a, int b)
{
return __atomic_compare_exchange (&v, &a, &b,
WEAK, __ATOMIC_RELEASE,
__ATOMIC_ACQUIRE);
}
int
atomic_compare_exchange_n_STRONG_RELEASE_ACQUIRE (int a, int b)
{
return __atomic_compare_exchange_n (&v, &a, b,
STRONG, __ATOMIC_RELEASE,
__ATOMIC_ACQUIRE);
}
int
atomic_compare_exchange_n_WEAK_RELEASE_ACQUIRE (int a, int b)
{
return __atomic_compare_exchange_n (&v, &a, b,
WEAK, __ATOMIC_RELEASE,
__ATOMIC_ACQUIRE);
}

38
gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c
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@ -1,43 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
int v = 0;
int
atomic_fetch_add_ACQ_REL (int a)
{
return __atomic_fetch_add (&v, a, __ATOMIC_ACQ_REL);
}
int
atomic_fetch_sub_ACQ_REL (int a)
{
return __atomic_fetch_sub (&v, a, __ATOMIC_ACQ_REL);
}
int
atomic_fetch_and_ACQ_REL (int a)
{
return __atomic_fetch_and (&v, a, __ATOMIC_ACQ_REL);
}
int
atomic_fetch_nand_ACQ_REL (int a)
{
return __atomic_fetch_nand (&v, a, __ATOMIC_ACQ_REL);
}
int
atomic_fetch_xor_ACQ_REL (int a)
{
return __atomic_fetch_xor (&v, a, __ATOMIC_ACQ_REL);
}
int
atomic_fetch_or_ACQ_REL (int a)
{
return __atomic_fetch_or (&v, a, __ATOMIC_ACQ_REL);
}
#include "atomic-op-acq_rel.x"
/* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */

37
gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.x Normal file
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@ -0,0 +1,37 @@
int v = 0;
int
atomic_fetch_add_ACQ_REL (int a)
{
return __atomic_fetch_add (&v, a, __ATOMIC_ACQ_REL);
}
int
atomic_fetch_sub_ACQ_REL (int a)
{
return __atomic_fetch_sub (&v, a, __ATOMIC_ACQ_REL);
}
int
atomic_fetch_and_ACQ_REL (int a)
{
return __atomic_fetch_and (&v, a, __ATOMIC_ACQ_REL);
}
int
atomic_fetch_nand_ACQ_REL (int a)
{
return __atomic_fetch_nand (&v, a, __ATOMIC_ACQ_REL);
}
int
atomic_fetch_xor_ACQ_REL (int a)
{
return __atomic_fetch_xor (&v, a, __ATOMIC_ACQ_REL);
}
int
atomic_fetch_or_ACQ_REL (int a)
{
return __atomic_fetch_or (&v, a, __ATOMIC_ACQ_REL);
}

38
gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c
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@ -1,43 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
int v = 0;
int
atomic_fetch_add_ACQUIRE (int a)
{
return __atomic_fetch_add (&v, a, __ATOMIC_ACQUIRE);
}
int
atomic_fetch_sub_ACQUIRE (int a)
{
return __atomic_fetch_sub (&v, a, __ATOMIC_ACQUIRE);
}
int
atomic_fetch_and_ACQUIRE (int a)
{
return __atomic_fetch_and (&v, a, __ATOMIC_ACQUIRE);
}
int
atomic_fetch_nand_ACQUIRE (int a)
{
return __atomic_fetch_nand (&v, a, __ATOMIC_ACQUIRE);
}
int
atomic_fetch_xor_ACQUIRE (int a)
{
return __atomic_fetch_xor (&v, a, __ATOMIC_ACQUIRE);
}
int
atomic_fetch_or_ACQUIRE (int a)
{
return __atomic_fetch_or (&v, a, __ATOMIC_ACQUIRE);
}
#include "atomic-op-acquire.x"
/* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */

37
gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.x Normal file
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@ -0,0 +1,37 @@
int v = 0;
int
atomic_fetch_add_ACQUIRE (int a)
{
return __atomic_fetch_add (&v, a, __ATOMIC_ACQUIRE);
}
int
atomic_fetch_sub_ACQUIRE (int a)
{
return __atomic_fetch_sub (&v, a, __ATOMIC_ACQUIRE);
}
int
atomic_fetch_and_ACQUIRE (int a)
{
return __atomic_fetch_and (&v, a, __ATOMIC_ACQUIRE);
}
int
atomic_fetch_nand_ACQUIRE (int a)
{
return __atomic_fetch_nand (&v, a, __ATOMIC_ACQUIRE);
}
int
atomic_fetch_xor_ACQUIRE (int a)
{
return __atomic_fetch_xor (&v, a, __ATOMIC_ACQUIRE);
}
int
atomic_fetch_or_ACQUIRE (int a)
{
return __atomic_fetch_or (&v, a, __ATOMIC_ACQUIRE);
}

38
gcc/testsuite/gcc.target/aarch64/atomic-op-char.c
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@ -1,43 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
char v = 0;
char
atomic_fetch_add_RELAXED (char a)
{
return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
}
char
atomic_fetch_sub_RELAXED (char a)
{
return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
}
char
atomic_fetch_and_RELAXED (char a)
{
return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
}
char
atomic_fetch_nand_RELAXED (char a)
{
return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
}
char
atomic_fetch_xor_RELAXED (char a)
{
return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
}
char
atomic_fetch_or_RELAXED (char a)
{
return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
}
#include "atomic-op-char.x"
/* { dg-final { scan-assembler-times "ldxrb\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "stxrb\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */

37
gcc/testsuite/gcc.target/aarch64/atomic-op-char.x Normal file
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@ -0,0 +1,37 @@
char v = 0;
char
atomic_fetch_add_RELAXED (char a)
{
return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
}
char
atomic_fetch_sub_RELAXED (char a)
{
return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
}
char
atomic_fetch_and_RELAXED (char a)
{
return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
}
char
atomic_fetch_nand_RELAXED (char a)
{
return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
}
char
atomic_fetch_xor_RELAXED (char a)
{
return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
}
char
atomic_fetch_or_RELAXED (char a)
{
return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
}

38
gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c
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@ -1,43 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
int v = 0;
int
atomic_fetch_add_CONSUME (int a)
{
return __atomic_fetch_add (&v, a, __ATOMIC_CONSUME);
}
int
atomic_fetch_sub_CONSUME (int a)
{
return __atomic_fetch_sub (&v, a, __ATOMIC_CONSUME);
}
int
atomic_fetch_and_CONSUME (int a)
{
return __atomic_fetch_and (&v, a, __ATOMIC_CONSUME);
}
int
atomic_fetch_nand_CONSUME (int a)
{
return __atomic_fetch_nand (&v, a, __ATOMIC_CONSUME);
}
int
atomic_fetch_xor_CONSUME (int a)
{
return __atomic_fetch_xor (&v, a, __ATOMIC_CONSUME);
}
int
atomic_fetch_or_CONSUME (int a)
{
return __atomic_fetch_or (&v, a, __ATOMIC_CONSUME);
}
#include "atomic-op-consume.x"
/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */

37
gcc/testsuite/gcc.target/aarch64/atomic-op-consume.x Normal file
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@ -0,0 +1,37 @@
int v = 0;
int
atomic_fetch_add_CONSUME (int a)
{
return __atomic_fetch_add (&v, a, __ATOMIC_CONSUME);
}
int
atomic_fetch_sub_CONSUME (int a)
{
return __atomic_fetch_sub (&v, a, __ATOMIC_CONSUME);
}
int
atomic_fetch_and_CONSUME (int a)
{
return __atomic_fetch_and (&v, a, __ATOMIC_CONSUME);
}
int
atomic_fetch_nand_CONSUME (int a)
{
return __atomic_fetch_nand (&v, a, __ATOMIC_CONSUME);
}
int
atomic_fetch_xor_CONSUME (int a)
{
return __atomic_fetch_xor (&v, a, __ATOMIC_CONSUME);
}
int
atomic_fetch_or_CONSUME (int a)
{
return __atomic_fetch_or (&v, a, __ATOMIC_CONSUME);
}

38
gcc/testsuite/gcc.target/aarch64/atomic-op-int.c
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@ -1,43 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
int v = 0;
int
atomic_fetch_add_RELAXED (int a)
{
return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
}
int
atomic_fetch_sub_RELAXED (int a)
{
return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
}
int
atomic_fetch_and_RELAXED (int a)
{
return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
}
int
atomic_fetch_nand_RELAXED (int a)
{
return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
}
int
atomic_fetch_xor_RELAXED (int a)
{
return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
}
int
atomic_fetch_or_RELAXED (int a)
{
return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
}
#include "atomic-op-int.x"
/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */

37
gcc/testsuite/gcc.target/aarch64/atomic-op-int.x Normal file
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@ -0,0 +1,37 @@
int v = 0;
int
atomic_fetch_add_RELAXED (int a)
{
return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
}
int
atomic_fetch_sub_RELAXED (int a)
{
return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
}
int
atomic_fetch_and_RELAXED (int a)
{
return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
}
int
atomic_fetch_nand_RELAXED (int a)
{
return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
}
int
atomic_fetch_xor_RELAXED (int a)
{
return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
}
int
atomic_fetch_or_RELAXED (int a)
{
return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
}

38
gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c
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@ -1,43 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
int v = 0;
int
atomic_fetch_add_RELAXED (int a)
{
return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
}
int
atomic_fetch_sub_RELAXED (int a)
{
return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
}
int
atomic_fetch_and_RELAXED (int a)
{
return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
}
int
atomic_fetch_nand_RELAXED (int a)
{
return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
}
int
atomic_fetch_xor_RELAXED (int a)
{
return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
}
int
atomic_fetch_or_RELAXED (int a)
{
return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
}
#include "atomic-op-relaxed.x"
/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */

37
gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.x Normal file
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@ -0,0 +1,37 @@
int v = 0;
int
atomic_fetch_add_RELAXED (int a)
{
return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
}
int
atomic_fetch_sub_RELAXED (int a)
{
return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
}
int
atomic_fetch_and_RELAXED (int a)
{
return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
}
int
atomic_fetch_nand_RELAXED (int a)
{
return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
}
int
atomic_fetch_xor_RELAXED (int a)
{
return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
}
int
atomic_fetch_or_RELAXED (int a)
{
return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
}

38
gcc/testsuite/gcc.target/aarch64/atomic-op-release.c
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@ -1,43 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
int v = 0;
int
atomic_fetch_add_RELEASE (int a)
{
return __atomic_fetch_add (&v, a, __ATOMIC_RELEASE);
}
int
atomic_fetch_sub_RELEASE (int a)
{
return __atomic_fetch_sub (&v, a, __ATOMIC_RELEASE);
}
int
atomic_fetch_and_RELEASE (int a)
{
return __atomic_fetch_and (&v, a, __ATOMIC_RELEASE);
}
int
atomic_fetch_nand_RELEASE (int a)
{
return __atomic_fetch_nand (&v, a, __ATOMIC_RELEASE);
}
int
atomic_fetch_xor_RELEASE (int a)
{
return __atomic_fetch_xor (&v, a, __ATOMIC_RELEASE);
}
int
atomic_fetch_or_RELEASE (int a)
{
return __atomic_fetch_or (&v, a, __ATOMIC_RELEASE);
}
#include "atomic-op-release.x"
/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */

37
gcc/testsuite/gcc.target/aarch64/atomic-op-release.x Normal file
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@ -0,0 +1,37 @@
int v = 0;
int
atomic_fetch_add_RELEASE (int a)
{
return __atomic_fetch_add (&v, a, __ATOMIC_RELEASE);
}
int
atomic_fetch_sub_RELEASE (int a)
{
return __atomic_fetch_sub (&v, a, __ATOMIC_RELEASE);
}
int
atomic_fetch_and_RELEASE (int a)
{
return __atomic_fetch_and (&v, a, __ATOMIC_RELEASE);
}
int
atomic_fetch_nand_RELEASE (int a)
{
return __atomic_fetch_nand (&v, a, __ATOMIC_RELEASE);
}
int
atomic_fetch_xor_RELEASE (int a)
{
return __atomic_fetch_xor (&v, a, __ATOMIC_RELEASE);
}
int
atomic_fetch_or_RELEASE (int a)
{
return __atomic_fetch_or (&v, a, __ATOMIC_RELEASE);
}

38
gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c
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@ -1,43 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
int v = 0;
int
atomic_fetch_add_SEQ_CST (int a)
{
return __atomic_fetch_add (&v, a, __ATOMIC_SEQ_CST);
}
int
atomic_fetch_sub_SEQ_CST (int a)
{
return __atomic_fetch_sub (&v, a, __ATOMIC_SEQ_CST);
}
int
atomic_fetch_and_SEQ_CST (int a)
{
return __atomic_fetch_and (&v, a, __ATOMIC_SEQ_CST);
}
int
atomic_fetch_nand_SEQ_CST (int a)
{
return __atomic_fetch_nand (&v, a, __ATOMIC_SEQ_CST);
}
int
atomic_fetch_xor_SEQ_CST (int a)
{
return __atomic_fetch_xor (&v, a, __ATOMIC_SEQ_CST);
}
int
atomic_fetch_or_SEQ_CST (int a)
{
return __atomic_fetch_or (&v, a, __ATOMIC_SEQ_CST);
}
#include "atomic-op-seq_cst.x"
/* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */

37
gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.x Normal file
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@ -0,0 +1,37 @@
int v = 0;
int
atomic_fetch_add_SEQ_CST (int a)
{
return __atomic_fetch_add (&v, a, __ATOMIC_SEQ_CST);
}
int
atomic_fetch_sub_SEQ_CST (int a)
{
return __atomic_fetch_sub (&v, a, __ATOMIC_SEQ_CST);
}
int
atomic_fetch_and_SEQ_CST (int a)
{
return __atomic_fetch_and (&v, a, __ATOMIC_SEQ_CST);
}
int
atomic_fetch_nand_SEQ_CST (int a)
{
return __atomic_fetch_nand (&v, a, __ATOMIC_SEQ_CST);
}
int
atomic_fetch_xor_SEQ_CST (int a)
{
return __atomic_fetch_xor (&v, a, __ATOMIC_SEQ_CST);
}
int
atomic_fetch_or_SEQ_CST (int a)
{
return __atomic_fetch_or (&v, a, __ATOMIC_SEQ_CST);
}

38
gcc/testsuite/gcc.target/aarch64/atomic-op-short.c
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@ -1,43 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
short v = 0;
short
atomic_fetch_add_RELAXED (short a)
{
return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
}
short
atomic_fetch_sub_RELAXED (short a)
{
return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
}
short
atomic_fetch_and_RELAXED (short a)
{
return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
}
short
atomic_fetch_nand_RELAXED (short a)
{
return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
}
short
atomic_fetch_xor_RELAXED (short a)
{
return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
}
short
atomic_fetch_or_RELAXED (short a)
{
return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
}
#include "atomic-op-short.x"
/* { dg-final { scan-assembler-times "ldxrh\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "stxrh\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */

37
gcc/testsuite/gcc.target/aarch64/atomic-op-short.x Normal file
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short v = 0;
short
atomic_fetch_add_RELAXED (short a)
{
return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
}
short
atomic_fetch_sub_RELAXED (short a)
{
return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
}
short
atomic_fetch_and_RELAXED (short a)
{
return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
}
short
atomic_fetch_nand_RELAXED (short a)
{
return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
}
short
atomic_fetch_xor_RELAXED (short a)
{
return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
}
short
atomic_fetch_or_RELAXED (short a)
{
return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
}

10
gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c Normal file
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/* { dg-require-effective-target arm_arch_v8a_ok } */
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-add-options arm_arch_v8a } */
#include "../aarch64/atomic-comp-swap-release-acquire.x"
/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 4 } } */
/* { dg-final { scan-assembler-times "stlex" 4 } } */
/* { dg-final { scan-assembler-not "dmb" } } */

10
gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c Normal file
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@ -0,0 +1,10 @@
/* { dg-require-effective-target arm_arch_v8a_ok } */
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-add-options arm_arch_v8a } */
#include "../aarch64/atomic-op-acq_rel.x"
/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-not "dmb" } } */

10
gcc/testsuite/gcc.target/arm/atomic-op-acquire.c Normal file
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@ -0,0 +1,10 @@
/* { dg-require-effective-target arm_arch_v8a_ok } */
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-add-options arm_arch_v8a } */
#include "../aarch64/atomic-op-acquire.x"
/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-not "dmb" } } */

10
gcc/testsuite/gcc.target/arm/atomic-op-char.c Normal file
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@ -0,0 +1,10 @@
/* { dg-require-effective-target arm_arch_v8a_ok } */
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-add-options arm_arch_v8a } */
#include "../aarch64/atomic-op-char.x"
/* { dg-final { scan-assembler-times "ldrexb\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "strexb\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-not "dmb" } } */

10
gcc/testsuite/gcc.target/arm/atomic-op-consume.c Normal file
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@ -0,0 +1,10 @@
/* { dg-require-effective-target arm_arch_v8a_ok } */
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-add-options arm_arch_v8a } */
#include "../aarch64/atomic-op-consume.x"
/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-not "dmb" } } */

10
gcc/testsuite/gcc.target/arm/atomic-op-int.c Normal file
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@ -0,0 +1,10 @@
/* { dg-require-effective-target arm_arch_v8a_ok } */
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-add-options arm_arch_v8a } */
#include "../aarch64/atomic-op-int.x"
/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-not "dmb" } } */

10
gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c Normal file
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@ -0,0 +1,10 @@
/* { dg-require-effective-target arm_arch_v8a_ok } */
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-add-options arm_arch_v8a } */
#include "../aarch64/atomic-op-relaxed.x"
/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-not "dmb" } } */

10
gcc/testsuite/gcc.target/arm/atomic-op-release.c Normal file
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@ -0,0 +1,10 @@
/* { dg-require-effective-target arm_arch_v8a_ok } */
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-add-options arm_arch_v8a } */
#include "../aarch64/atomic-op-release.x"
/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-not "dmb" } } */

10
gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c Normal file
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@ -0,0 +1,10 @@
/* { dg-require-effective-target arm_arch_v8a_ok } */
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-add-options arm_arch_v8a } */
#include "../aarch64/atomic-op-seq_cst.x"
/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-not "dmb" } } */

10
gcc/testsuite/gcc.target/arm/atomic-op-short.c Normal file
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@ -0,0 +1,10 @@
/* { dg-require-effective-target arm_arch_v8a_ok } */
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-add-options arm_arch_v8a } */
#include "../aarch64/atomic-op-short.x"
/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-not "dmb" } } */