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Turn on SEE unaligned load and store for Haswell

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PR target/59088
	* config/i386/x86-tune.def (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL):
	Set for m_HASWELL.
	(X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Set for m_HASWELL.

From-SVN: r204701
This commit is contained in:
H.J. Lu 2013-11-12 13:52:08 +00:00 committed by H.J. Lu
parent cd3c1b1c70
commit a720b48e18
2 changed files with 9 additions and 2 deletions
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7
gcc/ChangeLog
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@ -1,3 +1,10 @@
2013-11-12 H.J. Lu <hongjiu.lu@intel.com>
PR target/59088
* config/i386/x86-tune.def (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL):
Set for m_HASWELL.
(X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Set for m_HASWELL.
2013-11-12 H.J. Lu <hongjiu.lu@intel.com>
PR target/59084

4
gcc/config/i386/x86-tune.def
View File

@ -318,12 +318,12 @@ DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL, "general_regs_sse_spill",
/* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL: Use movups for misaligned loads instead
of a sequence loading registers by parts. */
DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal",
m_COREI7 | m_COREI7_AVX | m_AMDFAM10 | m_BDVER | m_BTVER | m_SLM | m_GENERIC)
m_COREI7 | m_COREI7_AVX | m_HASWELL | m_AMDFAM10 | m_BDVER | m_BTVER | m_SLM | m_GENERIC)
/* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores instead
of a sequence loading registers by parts. */
DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal",
m_COREI7 | m_COREI7_AVX | m_BDVER | m_SLM | m_GENERIC)
m_COREI7 | m_COREI7_AVX | m_HASWELL | m_BDVER | m_SLM | m_GENERIC)
/* Use packed single precision instructions where posisble. I.e. movups instead
of movupd. */