avr.md: Resolve all AS1 and AS2 macros.
* config/avr/avr.md: Resolve all AS1 and AS2 macros. Transform all "* quoted-c-code" to { c-code }. Remove redundant test for "optimize" in combine patterns. Move (include "avr-dimode.md") to end of file. From-SVN: r183739
This commit is contained in:
parent
03beeffe55
commit
a7fd5c6b06
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@ -1,3 +1,10 @@
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2012-01-30 Georg-Johann Lay <avr@gjlay.de>
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* config/avr/avr.md: Resolve all AS1 and AS2 macros.
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Transform all "* quoted-c-code" to { c-code }.
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Remove redundant test for "optimize" in combine patterns.
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Move (include "avr-dimode.md") to end of file.
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2012-01-30 Bin Cheng <bin.cheng@arm.com>
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2012-01-30 Bin Cheng <bin.cheng@arm.com>
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PR target/51835
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PR target/51835
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@ -1346,13 +1346,13 @@
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(mult:QI (match_operand:QI 1 "register_operand" "")
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(mult:QI (match_operand:QI 1 "register_operand" "")
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(match_operand:QI 2 "register_operand" "")))]
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(match_operand:QI 2 "register_operand" "")))]
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""
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""
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"{
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{
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if (!AVR_HAVE_MUL)
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if (!AVR_HAVE_MUL)
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{
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{
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emit_insn (gen_mulqi3_call (operands[0], operands[1], operands[2]));
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emit_insn (gen_mulqi3_call (operands[0], operands[1], operands[2]));
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DONE;
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DONE;
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}
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}
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}")
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})
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(define_insn "*mulqi3_enh"
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(define_insn "*mulqi3_enh"
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[(set (match_operand:QI 0 "register_operand" "=r")
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[(set (match_operand:QI 0 "register_operand" "=r")
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@ -4381,7 +4381,9 @@
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(label_ref (match_operand 3 "" ""))
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(label_ref (match_operand 3 "" ""))
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(pc)))]
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(pc)))]
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""
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""
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"* return avr_out_sbxx_branch (insn, operands);"
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{
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return avr_out_sbxx_branch (insn, operands);
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}
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[(set (attr "length")
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[(set (attr "length")
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(if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
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(if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
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(le (minus (pc) (match_dup 3)) (const_int 2046)))
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(le (minus (pc) (match_dup 3)) (const_int 2046)))
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@ -4559,8 +4561,9 @@
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(label_ref (match_operand 0 "" ""))
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(label_ref (match_operand 0 "" ""))
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(pc)))]
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(pc)))]
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""
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""
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"*
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{
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return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);"
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return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 0);
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}
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[(set_attr "type" "branch1")
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[(set_attr "type" "branch1")
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(set_attr "cc" "clobber")])
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(set_attr "cc" "clobber")])
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@ -4574,8 +4577,9 @@
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(pc)
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(pc)
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(label_ref (match_operand 0 "" ""))))]
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(label_ref (match_operand 0 "" ""))))]
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""
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""
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"*
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{
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return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);"
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return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);
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}
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[(set_attr "type" "branch1")
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[(set_attr "type" "branch1")
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(set_attr "cc" "clobber")])
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(set_attr "cc" "clobber")])
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@ -4587,8 +4591,9 @@
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(pc)
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(pc)
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(label_ref (match_operand 0 "" ""))))]
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(label_ref (match_operand 0 "" ""))))]
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""
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""
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"*
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{
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return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);"
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return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);
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}
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[(set_attr "type" "branch")
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[(set_attr "type" "branch")
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(set_attr "cc" "clobber")])
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(set_attr "cc" "clobber")])
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@ -4769,10 +4774,9 @@
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(use (label_ref (match_dup 3)))
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(use (label_ref (match_dup 3)))
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(clobber (match_dup 6))])]
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(clobber (match_dup 6))])]
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""
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""
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"
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{
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{
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operands[6] = gen_reg_rtx (HImode);
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operands[6] = gen_reg_rtx (HImode);
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}")
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})
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;; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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;; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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@ -4791,7 +4795,7 @@
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[(set (mem:QI (match_operand 0 "low_io_address_operand" "n"))
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[(set (mem:QI (match_operand 0 "low_io_address_operand" "n"))
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(and:QI (mem:QI (match_dup 0))
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(and:QI (mem:QI (match_dup 0))
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(match_operand:QI 1 "single_zero_operand" "n")))]
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(match_operand:QI 1 "single_zero_operand" "n")))]
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"optimize > 0"
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""
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{
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{
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operands[2] = GEN_INT (exact_log2 (~INTVAL (operands[1]) & 0xff));
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operands[2] = GEN_INT (exact_log2 (~INTVAL (operands[1]) & 0xff));
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return "cbi %i0,%2";
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return "cbi %i0,%2";
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@ -4803,7 +4807,7 @@
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[(set (mem:QI (match_operand 0 "low_io_address_operand" "n"))
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[(set (mem:QI (match_operand 0 "low_io_address_operand" "n"))
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(ior:QI (mem:QI (match_dup 0))
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(ior:QI (mem:QI (match_dup 0))
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(match_operand:QI 1 "single_one_operand" "n")))]
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(match_operand:QI 1 "single_one_operand" "n")))]
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"optimize > 0"
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""
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{
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{
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operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff));
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operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff));
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return "sbi %i0,%2";
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return "sbi %i0,%2";
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@ -4823,8 +4827,10 @@
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(const_int 0)])
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(const_int 0)])
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(label_ref (match_operand 3 "" ""))
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(label_ref (match_operand 3 "" ""))
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(pc)))]
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(pc)))]
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"(optimize > 0)"
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""
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"* return avr_out_sbxx_branch (insn, operands);"
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{
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return avr_out_sbxx_branch (insn, operands);
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}
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[(set (attr "length")
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[(set (attr "length")
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(if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
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(if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
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(le (minus (pc) (match_dup 3)) (const_int 2046)))
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(le (minus (pc) (match_dup 3)) (const_int 2046)))
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@ -4843,7 +4849,7 @@
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(const_int 0)])
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(const_int 0)])
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(label_ref (match_operand 2 "" ""))
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(label_ref (match_operand 2 "" ""))
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(pc)))]
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(pc)))]
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"(optimize > 0)"
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""
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{
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{
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operands[3] = operands[2];
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operands[3] = operands[2];
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operands[2] = GEN_INT (7);
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operands[2] = GEN_INT (7);
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@ -4870,8 +4876,10 @@
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(const_int 0)])
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(const_int 0)])
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(label_ref (match_operand 3 "" ""))
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(label_ref (match_operand 3 "" ""))
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(pc)))]
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(pc)))]
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"(optimize > 0)"
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""
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"* return avr_out_sbxx_branch (insn, operands);"
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{
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return avr_out_sbxx_branch (insn, operands);
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}
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[(set (attr "length")
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[(set (attr "length")
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(if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
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(if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
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(le (minus (pc) (match_dup 3)) (const_int 2045)))
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(le (minus (pc) (match_dup 3)) (const_int 2045)))
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@ -4889,7 +4897,7 @@
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(const_int 0)])
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(const_int 0)])
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(label_ref (match_operand 2 "" ""))
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(label_ref (match_operand 2 "" ""))
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(pc)))]
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(pc)))]
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"(optimize > 0)"
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""
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{
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{
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operands[3] = operands[2];
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operands[3] = operands[2];
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operands[2] = GEN_INT (7);
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operands[2] = GEN_INT (7);
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@ -4924,26 +4932,27 @@
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{
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{
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CC_STATUS_INIT;
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CC_STATUS_INIT;
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if (test_hard_reg_class (ADDW_REGS, operands[0]))
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if (test_hard_reg_class (ADDW_REGS, operands[0]))
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output_asm_insn (AS2 (sbiw,%0,1) CR_TAB
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output_asm_insn ("sbiw %0,1" CR_TAB
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AS2 (sbc,%C0,__zero_reg__) CR_TAB
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"sbc %C0,__zero_reg__" CR_TAB
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AS2 (sbc,%D0,__zero_reg__) "\n", operands);
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"sbc %D0,__zero_reg__", operands);
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else
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else
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output_asm_insn (AS2 (subi,%A0,1) CR_TAB
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output_asm_insn ("subi %A0,1" CR_TAB
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AS2 (sbc,%B0,__zero_reg__) CR_TAB
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"sbc %B0,__zero_reg__" CR_TAB
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AS2 (sbc,%C0,__zero_reg__) CR_TAB
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"sbc %C0,__zero_reg__" CR_TAB
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AS2 (sbc,%D0,__zero_reg__) "\n", operands);
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"sbc %D0,__zero_reg__", operands);
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switch (avr_jump_mode (operands[2], insn))
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switch (avr_jump_mode (operands[2], insn))
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{
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{
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case 1:
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case 1:
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return AS1 (brcc,%2);
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return "brcc %2";
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case 2:
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case 2:
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return (AS1 (brcs,.+2) CR_TAB
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return "brcs .+2\;rjmp %2";
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AS1 (rjmp,%2));
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case 3:
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return "brcs .+4\;jmp %2";
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}
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}
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return (AS1 (brcs,.+4) CR_TAB
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gcc_unreachable();
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AS1 (jmp,%2));
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return "";
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})
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})
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(define_peephole
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(define_peephole
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@ -4960,25 +4969,27 @@
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(label_ref (match_operand 2 "" ""))
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(label_ref (match_operand 2 "" ""))
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(pc)))]
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(pc)))]
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""
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""
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"*
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{
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{
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CC_STATUS_INIT;
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CC_STATUS_INIT;
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if (test_hard_reg_class (ADDW_REGS, operands[0]))
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if (test_hard_reg_class (ADDW_REGS, operands[0]))
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output_asm_insn (AS2 (sbiw,%0,1), operands);
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output_asm_insn ("sbiw %0,1", operands);
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else
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else
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output_asm_insn (AS2 (subi,%A0,1) CR_TAB
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output_asm_insn ("subi %A0,1" CR_TAB
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AS2 (sbc,%B0,__zero_reg__) \"\\n\", operands);
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"sbc %B0,__zero_reg__", operands);
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switch (avr_jump_mode (operands[2], insn))
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switch (avr_jump_mode (operands[2], insn))
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{
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{
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case 1:
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case 1:
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return AS1 (brcc,%2);
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return "brcc %2";
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case 2:
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case 2:
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return (AS1 (brcs,.+2) CR_TAB
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return "brcs .+2\;rjmp %2";
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AS1 (rjmp,%2));
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case 3:
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return "brcs .+4\;jmp %2";
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}
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}
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return (AS1 (brcs,.+4) CR_TAB
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AS1 (jmp,%2));
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gcc_unreachable();
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}")
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return "";
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})
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(define_peephole
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(define_peephole
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[(set (match_operand:QI 0 "d_register_operand" "")
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[(set (match_operand:QI 0 "d_register_operand" "")
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@ -4992,23 +5003,26 @@
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(label_ref (match_operand 1 "" ""))
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(label_ref (match_operand 1 "" ""))
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(pc)))]
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(pc)))]
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""
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""
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"*
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{
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{
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CC_STATUS_INIT;
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CC_STATUS_INIT;
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cc_status.value1 = operands[0];
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cc_status.value1 = operands[0];
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cc_status.flags |= CC_OVERFLOW_UNUSABLE;
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cc_status.flags |= CC_OVERFLOW_UNUSABLE;
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output_asm_insn (AS2 (subi,%A0,1), operands);
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output_asm_insn ("subi %A0,1", operands);
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switch (avr_jump_mode (operands[1], insn))
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switch (avr_jump_mode (operands[1], insn))
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{
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{
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case 1:
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case 1:
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return AS1 (brcc,%1);
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return "brcc %1";
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case 2:
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case 2:
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return (AS1 (brcs,.+2) CR_TAB
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return "brcs .+2\;rjmp %1";
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AS1 (rjmp,%1));
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case 3:
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return "brcs .+4\;jmp %1";
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}
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}
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return (AS1 (brcs,.+4) CR_TAB
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AS1 (jmp,%1));
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gcc_unreachable();
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}")
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return "";
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})
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(define_peephole ; "*cpse.eq"
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(define_peephole ; "*cpse.eq"
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operands[4] = simplify_gen_subreg (QImode, operands[0], HImode, 1);
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operands[4] = simplify_gen_subreg (QImode, operands[0], HImode, 1);
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})
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})
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(include "avr-dimode.md")
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(define_insn_and_split "*extzv.qihi2"
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(define_insn_and_split "*extzv.qihi2"
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[(set (match_operand:HI 0 "register_operand" "=r")
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[(set (match_operand:HI 0 "register_operand" "=r")
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(zero_extend:HI
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(zero_extend:HI
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operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, 0);
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operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, 0);
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operands[4] = simplify_gen_subreg (QImode, operands[0], HImode, 1);
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operands[4] = simplify_gen_subreg (QImode, operands[0], HImode, 1);
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})
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})
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(include "avr-dimode.md")
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