pa.c (pa_adjust_insn_length): dbra and movb insns which have their output in a FP register do not need adjustment.
* pa.c (pa_adjust_insn_length): dbra and movb insns which have
their output in a FP register do not need adjustment.
(output_cbranch, output_bb): Handle conditional jump to the
following instruction.
(output_dbra): New function extracted from dbra pattern.
(output_movb): New function.
(eq_neq_comparison_operator): New function.
(movb_comparison_operator): New function.
From-SVN: r4888
This commit is contained in:
Jeff Law
parent
98b2d88783
commit
b1a275e1e0
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@ -2543,10 +2543,12 @@ pa_adjust_insn_length (insn, length)
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&& ! forward_branch_p (insn))
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return 1;
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/* Adjust dbra insn with short backwards conditional branch with
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unfilled delay slot -- only for case where counter is in a register. */
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unfilled delay slot -- only for case where counter is in a
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general register register. */
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else if (GET_CODE (pat) == PARALLEL
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&& GET_CODE (XVECEXP (pat, 0, 1)) == SET
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&& GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
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&& ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
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&& length == 1
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&& ! forward_branch_p (insn))
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return 1;
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@ -3250,10 +3252,18 @@ output_cbranch (operands, nullify, length, negated, insn)
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rtx *operands;
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int nullify, length, negated;
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rtx insn;
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{
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{
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static char buf[100];
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int useskip = 0;
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/* A conditional branch to the following instruction (eg the delay slot) is
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asking for a disaster. This can happen when not optimizing.
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In such cases it is safe to emit nothing. */
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if (JUMP_LABEL (insn) == next_nonnote_insn (insn))
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return "";
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/* If this is a long branch with its delay slot unfilled, set `nullify'
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as it can nullify the delay slot and save a nop. */
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if (length == 2 && dbr_sequence_length () == 0)
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@ -3343,10 +3353,18 @@ output_bb (operands, nullify, length, negated, insn, which)
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int nullify, length, negated;
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rtx insn;
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int which;
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{
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{
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static char buf[100];
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int useskip = 0;
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/* A conditional branch to the following instruction (eg the delay slot) is
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asking for a disaster. I do not think this can happen as this pattern
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is only used when optimizing; jump optimization should eliminate the
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jump. But be prepared just in case. */
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if (JUMP_LABEL (insn) == next_nonnote_insn (insn))
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return "";
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/* If this is a long branch with its delay slot unfilled, set `nullify'
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as it can nullify the delay slot and save a nop. */
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if (length == 2 && dbr_sequence_length () == 0)
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@ -3441,6 +3459,197 @@ output_bb (operands, nullify, length, negated, insn, which)
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return buf;
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}
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/* Return the output template for emitting a dbra type insn.
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Note it may perform some output operations on its own before
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returning the final output string. */
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char *
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output_dbra (operands, insn, which_alternative)
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rtx *operands;
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rtx insn;
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int which_alternative;
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{
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/* A conditional branch to the following instruction (eg the delay slot) is
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asking for a disaster. Be prepared! */
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if (JUMP_LABEL (insn) == next_nonnote_insn (insn))
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{
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if (which_alternative == 0)
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return "ldo %1(%0),%0";
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else if (which_alternative == 1)
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{
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output_asm_insn ("fstws %0,-16(0,%%r30)",operands);
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output_asm_insn ("ldw -16(0,%%r30),%4",operands);
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output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(0,%%r30)", operands);
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return "fldws -16(0,%%r30),%0";
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}
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else
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{
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output_asm_insn ("ldw %0,%4", operands);
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return "ldo %1(%4),%4\n\tstw %4,%0";
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}
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}
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if (which_alternative == 0)
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{
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int nullify = INSN_ANNULLED_BRANCH_P (insn);
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int length = get_attr_length (insn);
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/* If this is a long branch with its delay slot unfilled, set `nullify'
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as it can nullify the delay slot and save a nop. */
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if (length == 2 && dbr_sequence_length () == 0)
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nullify = 1;
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/* If this is a short forward conditional branch which did not get
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its delay slot filled, the delay slot can still be nullified. */
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if (! nullify && length == 1 && dbr_sequence_length () == 0)
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nullify = forward_branch_p (insn);
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/* Handle short versions first. */
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if (length == 1 && nullify)
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return "addib,%C2,n %1,%0,%3";
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else if (length == 1 && ! nullify)
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return "addib,%C2 %1,%0,%3";
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else if (length == 2)
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{
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/* Handle weird backwards branch with a fulled delay slot
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which is nullified. */
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if (dbr_sequence_length () != 0
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&& ! forward_branch_p (insn)
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&& nullify)
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return "addib,%N2,n %1,%0,.+12\n\tbl %3,0";
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/* Handle normal cases. */
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if (nullify)
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return "addi,%N2 %1,%0,%0\n\tbl,n %3,0";
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else
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return "addi,%N2 %1,%0,%0\n\tbl %3,0";
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}
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else
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abort();
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}
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/* Deal with gross reload from FP register case. */
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else if (which_alternative == 1)
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{
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/* Move loop counter from FP register to MEM then into a GR,
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increment the GR, store the GR into MEM, and finally reload
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the FP register from MEM from within the branch's delay slot. */
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output_asm_insn ("fstws %0,-16(0,%%r30)\n\tldw -16(0,%%r30),%4",operands);
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output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(0,%%r30)", operands);
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if (get_attr_length (insn) == 6)
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return "comb,%S2 0,%4,%3\n\tfldws -16(0,%%r30),%0";
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else
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return "comclr,%B2 0,%4,0\n\tbl %3,0\n\tfldws -16(0,%%r30),%0";
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}
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/* Deal with gross reload from memory case. */
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else
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{
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/* Reload loop counter from memory, the store back to memory
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happens in the branch's delay slot. */
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output_asm_insn ("ldw %0,%4", operands);
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if (get_attr_length (insn) == 3)
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return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
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else
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return "addi,%N2 %1,%4,%0\n\tbl %3,0\n\tstw %4,%0";
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}
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}
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/* Return the output template for emitting a dbra type insn.
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Note it may perform some output operations on its own before
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returning the final output string. */
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char *
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output_movb (operands, insn, which_alternative, reverse_comparison)
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rtx *operands;
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rtx insn;
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int which_alternative;
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int reverse_comparison;
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{
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/* A conditional branch to the following instruction (eg the delay slot) is
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asking for a disaster. Be prepared! */
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if (JUMP_LABEL (insn) == next_nonnote_insn (insn))
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{
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if (which_alternative == 0)
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return "copy %1,%0";
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else if (which_alternative == 1)
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{
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output_asm_insn ("fstws %1,-16(0,%%r30)",operands);
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return "fldws -16(0,%%r30),%0";
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}
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else
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return "stw %1,%0";
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}
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/* Support the second variant. */
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if (reverse_comparison)
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PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
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if (which_alternative == 0)
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{
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int nullify = INSN_ANNULLED_BRANCH_P (insn);
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int length = get_attr_length (insn);
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/* If this is a long branch with its delay slot unfilled, set `nullify'
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as it can nullify the delay slot and save a nop. */
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if (length == 2 && dbr_sequence_length () == 0)
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nullify = 1;
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/* If this is a short forward conditional branch which did not get
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its delay slot filled, the delay slot can still be nullified. */
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if (! nullify && length == 1 && dbr_sequence_length () == 0)
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nullify = forward_branch_p (insn);
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/* Handle short versions first. */
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if (length == 1 && nullify)
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return "movb,%C2,n %1,%0,%3";
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else if (length == 1 && ! nullify)
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return "movb,%C2 %1,%0,%3";
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else if (length == 2)
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{
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/* Handle weird backwards branch with a fulled delay slot
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which is nullified. */
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if (dbr_sequence_length () != 0
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&& ! forward_branch_p (insn)
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&& nullify)
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return "movb,%N2,n %1,%0,.+12\n\ttbl %3,0";
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/* Handle normal cases. */
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if (nullify)
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return "or,%N2 %1,%%r0,%0\n\tbl,n %3,0";
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else
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return "or,%N2 %1,%%r0,%0\n\tbl %3,0";
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}
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else
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abort();
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}
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/* Deal with gross reload from FP register case. */
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else if (which_alternative == 1)
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{
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/* Move loop counter from FP register to MEM then into a GR,
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increment the GR, store the GR into MEM, and finally reload
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the FP register from MEM from within the branch's delay slot. */
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output_asm_insn ("fstws %1,-16(0,%%r30)",operands);
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if (get_attr_length (insn) == 3)
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return "comb,%S2 0,%1,%3\n\tfldws -16(0,%%r30),%0";
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else
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return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tfldws -16(0,%%r30),%0";
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}
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/* Deal with gross reload from memory case. */
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else
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{
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/* Reload loop counter from memory, the store back to memory
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happens in the branch's delay slot. */
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if (get_attr_length (insn) == 2)
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return "comb,%S2 0,%1,%3\n\tstw %1,%0";
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else
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return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tstw %1,%0";
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}
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}
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extern struct obstack *saveable_obstack;
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/* In HPUX 8.0's shared library scheme, special relocations are needed
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@ -3603,3 +3812,22 @@ forward_branch_p (insn)
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return (insn == label);
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}
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/* Return 1 if OP is an equality comparison, else return 0. */
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int
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eq_neq_comparison_operator (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
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}
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/* Return 1 if OP is an operator suitable for use in a movb instruction. */
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int
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movb_comparison_operator (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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return (GET_CODE (op) == EQ || GET_CODE (op) == NE
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|| GET_CODE (op) == LT || GET_CODE (op) == GE);
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}
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