i386.c (pentium4_cost): New.
* i386.c (pentium4_cost): New. (m_PENT4): New macro. (x86_push_memory, x86_movx,x86_cmove, x86_deep_branch, x86_use_sahf x86_sub_esp_4, x86_sub_esp_8, x86_add_esp_4, x86_add_esp_8 x86_integer_DFmode_moves, x86_partial_reg_dependency, x86_memory_mismatch_stall): Add Pentium4 (x86_use_q_reg, x86_use_any_reg): Kill. (override_options): Add pentium4. (incdec_operand): Return 0 for pentium4. (ix86_issue_rate): Add PROCESSOR_PENTIUM4 and PROCESSOR_ATHLON. * i386.h (x86_use_q_reg, x86_use_any_reg): Kill. (TARGET_PENTIUM4): Define. (enum processor_type): Add PROCESSOR_PENTIUM4. (CPP_CPU_DEFAULT_SPEC): Add pentium4 support. * i386.md (attribute "cpu"): Add pentium4. * invoke.texi (march): Add pentium4. From-SVN: r40134
This commit is contained in:
Jan Hubicka
Jan Hubicka
parent
0073023dde
commit
b4e89e2d67
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@ -1,3 +1,22 @@
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Wed Feb 28 19:31:42 CET 2001 Jan Hubicka <jh@suse.cz>
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* i386.c (pentium4_cost): New.
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(m_PENT4): New macro.
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(x86_push_memory, x86_movx,x86_cmove, x86_deep_branch, x86_use_sahf
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x86_sub_esp_4, x86_sub_esp_8, x86_add_esp_4, x86_add_esp_8
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x86_integer_DFmode_moves, x86_partial_reg_dependency,
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x86_memory_mismatch_stall): Add Pentium4
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(x86_use_q_reg, x86_use_any_reg): Kill.
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(override_options): Add pentium4.
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(incdec_operand): Return 0 for pentium4.
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(ix86_issue_rate): Add PROCESSOR_PENTIUM4 and PROCESSOR_ATHLON.
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* i386.h (x86_use_q_reg, x86_use_any_reg): Kill.
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(TARGET_PENTIUM4): Define.
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(enum processor_type): Add PROCESSOR_PENTIUM4.
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(CPP_CPU_DEFAULT_SPEC): Add pentium4 support.
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* i386.md (attribute "cpu"): Add pentium4.
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* invoke.texi (march): Add pentium4.
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Wed Feb 28 19:28:06 CET 2001 Jan Hubicka <jh@suse.cz>
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* i386.md (sse_mov?fcc*): New patterns and splitters.
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@ -239,6 +239,38 @@ struct processor_costs athlon_cost = {
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6 /* MMX or SSE register to integer */
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};
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struct processor_costs pentium4_cost = {
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1, /* cost of an add instruction */
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1, /* cost of a lea instruction */
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8, /* variable shift costs */
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8, /* constant shift costs */
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30, /* cost of starting a multiply */
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0, /* cost of multiply per each bit set */
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112, /* cost of a divide/mod */
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16, /* "large" insn */
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6, /* MOVE_RATIO */
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2, /* cost for loading QImode using movzbl */
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{4, 5, 4}, /* cost of loading integer registers
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in QImode, HImode and SImode.
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Relative to reg-reg move (2). */
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{2, 3, 2}, /* cost of storing integer registers */
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2, /* cost of reg,reg fld/fst */
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{2, 2, 6}, /* cost of loading fp registers
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in SFmode, DFmode and XFmode */
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{4, 4, 6}, /* cost of loading integer registers */
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2, /* cost of moving MMX register */
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{2, 2}, /* cost of loading MMX registers
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in SImode and DImode */
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{2, 2}, /* cost of storing MMX registers
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in SImode and DImode */
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12, /* cost of moving SSE register */
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{12, 12, 12}, /* cost of loading SSE registers
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in SImode, DImode and TImode */
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{2, 2, 8}, /* cost of storing SSE registers
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in SImode, DImode and TImode */
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10, /* MMX or SSE register to integer */
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};
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struct processor_costs *ix86_cost = &pentium_cost;
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/* Processor feature/optimization bitmasks. */
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@ -248,19 +280,18 @@ struct processor_costs *ix86_cost = &pentium_cost;
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#define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
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#define m_K6 (1<<PROCESSOR_K6)
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#define m_ATHLON (1<<PROCESSOR_ATHLON)
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#define m_PENT4 (1<<PROCESSOR_PENTIUM4)
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const int x86_use_leave = m_386 | m_K6 | m_ATHLON;
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const int x86_push_memory = m_386 | m_K6 | m_ATHLON;
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const int x86_push_memory = m_386 | m_K6 | m_ATHLON | m_PENT4;
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const int x86_zero_extend_with_and = m_486 | m_PENT;
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const int x86_movx = m_ATHLON | m_PPRO /* m_386 | m_K6 */;
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const int x86_movx = m_ATHLON | m_PPRO | m_PENT4 /* m_386 | m_K6 */;
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const int x86_double_with_add = ~m_386;
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const int x86_use_bit_test = m_386;
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const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON | m_K6;
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const int x86_use_q_reg = m_PENT | m_PPRO | m_K6;
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const int x86_use_any_reg = m_486;
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const int x86_cmove = m_PPRO | m_ATHLON;
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const int x86_deep_branch = m_PPRO | m_K6 | m_ATHLON;
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const int x86_use_sahf = m_PPRO | m_K6;
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const int x86_cmove = m_PPRO | m_ATHLON | m_PENT4;
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const int x86_deep_branch = m_PPRO | m_K6 | m_ATHLON | m_PENT4;
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const int x86_use_sahf = m_PPRO | m_K6 | m_PENT4;
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const int x86_partial_reg_stall = m_PPRO;
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const int x86_use_loop = m_K6;
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const int x86_use_fiop = ~(m_PPRO | m_ATHLON | m_PENT);
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@ -270,18 +301,18 @@ const int x86_read_modify_write = ~m_PENT;
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const int x86_read_modify = ~(m_PENT | m_PPRO);
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const int x86_split_long_moves = m_PPRO;
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const int x86_promote_QImode = m_K6 | m_PENT | m_386 | m_486;
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const int x86_single_stringop = m_386;
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const int x86_single_stringop = m_386 | m_PENT4;
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const int x86_qimode_math = ~(0);
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const int x86_promote_qi_regs = 0;
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const int x86_himode_math = ~(m_PPRO);
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const int x86_promote_hi_regs = m_PPRO;
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const int x86_sub_esp_4 = m_ATHLON | m_PPRO;
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const int x86_sub_esp_8 = m_ATHLON | m_PPRO | m_386 | m_486;
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const int x86_add_esp_4 = m_ATHLON | m_K6;
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const int x86_add_esp_8 = m_ATHLON | m_PPRO | m_K6 | m_386 | m_486;
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const int x86_integer_DFmode_moves = ~m_ATHLON;
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const int x86_partial_reg_dependency = m_ATHLON;
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const int x86_memory_mismatch_stall = m_ATHLON;
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const int x86_sub_esp_4 = m_ATHLON | m_PPRO | m_PENT4;
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const int x86_sub_esp_8 = m_ATHLON | m_PPRO | m_386 | m_486 | m_PENT4;
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const int x86_add_esp_4 = m_ATHLON | m_K6 | m_PENT4;
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const int x86_add_esp_8 = m_ATHLON | m_PPRO | m_K6 | m_386 | m_486 | m_PENT4;
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const int x86_integer_DFmode_moves = ~(m_ATHLON | m_PENT4);
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const int x86_partial_reg_dependency = m_ATHLON | m_PENT4;
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const int x86_memory_mismatch_stall = m_ATHLON | m_PENT4;
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#define AT_BP(mode) (gen_rtx_MEM ((mode), hard_frame_pointer_rtx))
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@ -577,7 +608,8 @@ override_options ()
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{&pentium_cost, 0, 0, -4, -4, -4, 1},
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{&pentiumpro_cost, 0, 0, 4, -4, 4, 1},
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{&k6_cost, 0, 0, -5, -5, 4, 1},
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{&athlon_cost, 0, 0, 4, -4, 4, 1}
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{&athlon_cost, 0, 0, 4, -4, 4, 1},
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{&pentium4_cost, 0, 0, 2, 2, 2, 1}
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};
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static struct pta
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@ -595,6 +627,7 @@ override_options ()
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{"pentiumpro", PROCESSOR_PENTIUMPRO},
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{"k6", PROCESSOR_K6},
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{"athlon", PROCESSOR_ATHLON},
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{"pentium4", PROCESSOR_PENTIUM4},
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};
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int const pta_size = sizeof (processor_alias_table) / sizeof (struct pta);
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@ -1202,6 +1235,10 @@ incdec_operand (op, mode)
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register rtx op;
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enum machine_mode mode;
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{
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/* On Pentium4, the inc and dec operations causes extra dependancy on flag
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registers, since carry flag is not set. */
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if (TARGET_PENTIUM4 && !optimize_size)
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return 0;
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if (op == const1_rtx || op == constm1_rtx)
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return 1;
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if (GET_CODE (op) != CONST_INT)
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@ -6900,6 +6937,8 @@ ix86_issue_rate ()
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return 2;
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case PROCESSOR_PENTIUMPRO:
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case PROCESSOR_PENTIUM4:
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case PROCESSOR_ATHLON:
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return 3;
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default:
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@ -184,11 +184,12 @@ extern int target_flags;
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#define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO)
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#define TARGET_K6 (ix86_cpu == PROCESSOR_K6)
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#define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON)
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#define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4)
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#define CPUMASK (1 << ix86_cpu)
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extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
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extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
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extern const int x86_unroll_strlen, x86_use_q_reg, x86_use_any_reg;
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extern const int x86_unroll_strlen;
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extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
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extern const int x86_use_loop, x86_use_fiop, x86_use_mov0;
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extern const int x86_use_cltd, x86_read_modify_write;
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@ -204,8 +205,6 @@ extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
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#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK)
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#define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK)
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#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
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#define TARGET_USE_Q_REG (x86_use_q_reg & CPUMASK)
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#define TARGET_USE_ANY_REG (x86_use_any_reg & CPUMASK)
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/* For sane SSE instruction set generation we need fcomi instruction. It is
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safe to enable all CMOVE instructions. */
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#define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
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@ -345,6 +344,7 @@ enum processor_type
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PROCESSOR_PENTIUMPRO,
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PROCESSOR_K6,
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PROCESSOR_ATHLON,
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PROCESSOR_PENTIUM4,
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PROCESSOR_max
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};
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@ -431,6 +431,9 @@ extern int ix86_arch;
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#if TARGET_CPU_DEFAULT == 5
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#define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__"
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#endif
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#if TARGET_CPU_DEFAULT == 6
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#define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__"
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#endif
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#ifndef CPP_CPU_DEFAULT_SPEC
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#define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__"
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#endif
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@ -449,12 +452,14 @@ extern int ix86_arch;
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%{!mcpu*:-D__tune_i686__ -D__tune_pentiumpro__ }}\
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%{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\
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%{march=athlon:-D__athlon -D__athlon__ %{!mcpu*:-D__tune_athlon__ }}\
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%{mpentium4=pentium4:-D__pentium4 -D__pentium4__ %{!mcpu*:-D__tune_pentium4__ }}\
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%{m386|mcpu=i386:-D__tune_i386__ }\
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%{m486|mcpu=i486:-D__tune_i486__ }\
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%{mpentium|mcpu=pentium|mcpu=i586:-D__tune_i586__ -D__tune_pentium__ }\
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%{mpentiumpro|mcpu=pentiumpro|mcpu=i686:-D__tune_i686__ -D__tune_pentiumpro__ }\
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%{mcpu=k6:-D__tune_k6__ }\
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%{mcpu=athlon:-D__tune_athlon__ }\
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%{mcpu=pentium4:-D__tune_pentium4__ }\
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%{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}"
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#endif
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@ -97,7 +97,7 @@
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;; Processor type. This attribute must exactly match the processor_type
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;; enumeration in i386.h.
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(define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon"
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(define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4"
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(const (symbol_ref "ix86_cpu")))
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;; A basic instruction type. Refinements due to arguments to be
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@ -6534,14 +6534,14 @@ These @samp{-m} options are defined for the i386 family of computers:
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Assume the defaults for the machine type @var{cpu type} when scheduling
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instructions. The choices for @var{cpu type} are @samp{i386},
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@samp{i486}, @samp{i586}, @samp{i686}, @samp{pentium},
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@samp{pentiumpro}, @samp{k6}, and @samp{athlon}
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@samp{pentiumpro}, @samp{pentium4}, @samp{k6}, and @samp{athlon}
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While picking a specific @var{cpu type} will schedule things appropriately
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for that particular chip, the compiler will not generate any code that
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does not run on the i386 without the @samp{-march=@var{cpu type}} option
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being used. @samp{i586} is equivalent to @samp{pentium} and @samp{i686}
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is equivalent to @samp{pentiumpro}. @samp{k6} is the AMD chip as
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opposed to the Intel ones.
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is equivalent to @samp{pentiumpro}. @samp{k6} and @samp{athlon} sre the
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AMD chips as opposed to the Intel ones.
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@item -march=@var{cpu type}
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Generate instructions for the machine type @var{cpu type}. The choices
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