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sse.md (<ssse3_avx2>_palignr<mode>): Use constraint x instead of v in second alternative, add avx512bw alternative. 

* config/i386/sse.md (<ssse3_avx2>_palignr<mode>): Use
	constraint x instead of v in second alternative, add avx512bw
	alternative.

	* gcc.target/i386/avx512vl-vpalignr-3.c: New test.
	* gcc.target/i386/avx512bw-vpalignr-3.c: New test.

From-SVN: r236368
This commit is contained in:
Jakub Jelinek 2016-05-18 11:24:15 +02:00 committed by Jakub Jelinek
parent a4f164221f
commit cf4d516a50
5 changed files with 75 additions and 7 deletions
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4
gcc/ChangeLog
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@ -1,5 +1,9 @@
2016-05-18 Jakub Jelinek <jakub@redhat.com>
* config/i386/sse.md (<ssse3_avx2>_palignr<mode>): Use
constraint x instead of v in second alternative, add avx512bw
alternative.
* config/i386/sse.md (<ssse3_avx2>_pshufb<mode>3<mask_name>): Use
constraint x instead of v in second alternative, add avx512bw
alternative.

15
gcc/config/i386/sse.md
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@ -14301,11 +14301,11 @@
(set_attr "mode" "<sseinsnmode>")])
(define_insn "<ssse3_avx2>_palignr<mode>"
[(set (match_operand:SSESCALARMODE 0 "register_operand" "=x,v")
[(set (match_operand:SSESCALARMODE 0 "register_operand" "=x,x,v")
(unspec:SSESCALARMODE
[(match_operand:SSESCALARMODE 1 "register_operand" "0,v")
(match_operand:SSESCALARMODE 2 "vector_operand" "xBm,vm")
(match_operand:SI 3 "const_0_to_255_mul_8_operand" "n,n")]
[(match_operand:SSESCALARMODE 1 "register_operand" "0,x,v")
(match_operand:SSESCALARMODE 2 "vector_operand" "xBm,xm,vm")
(match_operand:SI 3 "const_0_to_255_mul_8_operand" "n,n,n")]
UNSPEC_PALIGNR))]
"TARGET_SSSE3"
{
@ -14316,18 +14316,19 @@
case 0:
return "palignr\t{%3, %2, %0|%0, %2, %3}";
case 1:
case 2:
return "vpalignr\t{%3, %2, %1, %0|%0, %1, %2, %3}";
default:
gcc_unreachable ();
}
}
[(set_attr "isa" "noavx,avx")
[(set_attr "isa" "noavx,avx,avx512bw")
(set_attr "type" "sseishft")
(set_attr "atom_unit" "sishuf")
(set_attr "prefix_data16" "1,*")
(set_attr "prefix_data16" "1,*,*")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "orig,vex")
(set_attr "prefix" "orig,vex,evex")
(set_attr "mode" "<sseinsnmode>")])
(define_insn "ssse3_palignrdi"

3
gcc/testsuite/ChangeLog
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@ -1,5 +1,8 @@
2016-05-18 Jakub Jelinek <jakub@redhat.com>
* gcc.target/i386/avx512vl-vpalignr-3.c: New test.
* gcc.target/i386/avx512bw-vpalignr-3.c: New test.
* gcc.target/i386/avx512vl-vpshufb-3.c: New test.
* gcc.target/i386/avx512bw-vpshufb-3.c: New test.

30
gcc/testsuite/gcc.target/i386/avx512bw-vpalignr-3.c Normal file
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@ -0,0 +1,30 @@
/* { dg-do compile { target { ! ia32 } } } */
/* { dg-options "-O2 -mavx512vl -mavx512bw" } */
#include <x86intrin.h>
void
f1 (__m128i x, __m128i y)
{
register __m128i a __asm ("xmm16"), b __asm ("xmm17");
a = x;
b = y;
asm volatile ("" : "+v" (a), "+v" (b));
a = _mm_alignr_epi8 (a, b, 3);
asm volatile ("" : "+v" (a));
}
/* { dg-final { scan-assembler "vpalignr\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]" } } */
void
f2 (__m256i x, __m256i y)
{
register __m256i a __asm ("xmm16"), b __asm ("xmm17");
a = x;
b = y;
asm volatile ("" : "+v" (a), "+v" (b));
a = _mm256_alignr_epi8 (a, b, 3);
asm volatile ("" : "+v" (a));
}
/* { dg-final { scan-assembler "vpalignr\[^\n\r]*ymm1\[67]\[^\n\r]*ymm1\[67]\[^\n\r]*ymm1\[67]" } } */

30
gcc/testsuite/gcc.target/i386/avx512vl-vpalignr-3.c Normal file
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@ -0,0 +1,30 @@
/* { dg-do compile { target { ! ia32 } } } */
/* { dg-options "-O2 -mavx512vl -mno-avx512bw" } */
#include <x86intrin.h>
void
f1 (__m128i x, __m128i y)
{
register __m128i a __asm ("xmm16"), b __asm ("xmm17");
a = x;
b = y;
asm volatile ("" : "+v" (a), "+v" (b));
a = _mm_alignr_epi8 (a, b, 3);
asm volatile ("" : "+v" (a));
}
/* { dg-final { scan-assembler-not "vpalignr\[^\n\r]*xmm1\[67]" } } */
void
f2 (__m256i x, __m256i y)
{
register __m256i a __asm ("xmm16"), b __asm ("xmm17");
a = x;
b = y;
asm volatile ("" : "+v" (a), "+v" (b));
a = _mm256_alignr_epi8 (a, b, 3);
asm volatile ("" : "+v" (a));
}
/* { dg-final { scan-assembler-not "vpalignr\[^\n\r]*ymm1\[67]" } } */