[PATCH] RS6000 Add testlsbb by Byte operations
Add support for new instructions to test LSB by Byte. 2020-07-29 Will Schmidt <will_schmidt@vnet.ibm.com> gcc/ChangeLog: * config/rs6000/altivec.h (vec_test_lsbb_all_ones): New define. (vec_test_lsbb_all_zeros): New define. * config/rs6000/rs6000-builtin.def (BU_P10_VSX_1): New built-in handling macro. (XVTLSBB_ZEROS, XVTLSBB_ONES): New builtin defines. (xvtlsbb_all_zeros, xvtlsbb_all_ones): New builtin overloads. * config/rs6000/rs6000-call.c (P10_BUILTIN_VEC_XVTLSBB_ZEROS, P10_BUILTIN_VEC_XVTLSBB_ONES): New altivec_builtin_types entries. * config/rs6000/rs6000.md (UNSPEC_XVTLSBB): New unspec. * config/rs6000/vsx.md (*xvtlsbb_internal): New instruction define. (xvtlsbbo, xvtlsbbz): New instruction expands. gcc/testsuite/ChangeLog: * gcc.target/powerpc/lsbb-runnable.c: New test. * gcc.target/powerpc/lsbb.c: New test.
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Will Schmidt
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c931e8d5a9
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@ -493,6 +493,9 @@
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#define vec_cntlz_lsbb __builtin_vec_vclzlsbb
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#define vec_cnttz_lsbb __builtin_vec_vctzlsbb
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#define vec_test_lsbb_all_ones __builtin_vec_xvtlsbb_all_ones
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#define vec_test_lsbb_all_zeros __builtin_vec_xvtlsbb_all_zeros
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#define vec_xlx __builtin_vec_vextulx
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#define vec_xrx __builtin_vec_vexturx
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#endif
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@ -1062,6 +1062,14 @@
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| RS6000_BTC_QUATERNARY), \
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CODE_FOR_ ## ICODE) /* ICODE */
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#define BU_P10_VSX_1(ENUM, NAME, ATTR, ICODE) \
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RS6000_BUILTIN_1 (P10_BUILTIN_ ## ENUM, /* ENUM */ \
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"__builtin_vsx_" NAME, /* NAME */ \
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RS6000_BTM_P10, /* MASK */ \
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(RS6000_BTC_ ## ATTR /* ATTR */ \
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| RS6000_BTC_UNARY), \
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CODE_FOR_ ## ICODE) /* ICODE */
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#define BU_P10_OVERLOAD_1(ENUM, NAME) \
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RS6000_BUILTIN_1 (P10_BUILTIN_VEC_ ## ENUM, /* ENUM */ \
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"__builtin_vec_" NAME, /* NAME */ \
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@ -2736,6 +2744,9 @@ BU_P10V_1 (VSTRIHR_P, "vstrihr_p", CONST, vstrir_p_v8hi)
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BU_P10V_1 (VSTRIBL_P, "vstribl_p", CONST, vstril_p_v16qi)
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BU_P10V_1 (VSTRIHL_P, "vstrihl_p", CONST, vstril_p_v8hi)
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BU_P10_VSX_1 (XVTLSBB_ZEROS, "xvtlsbb_all_zeros", CONST, xvtlsbbz)
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BU_P10_VSX_1 (XVTLSBB_ONES, "xvtlsbb_all_ones", CONST, xvtlsbbo)
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BU_P10V_1 (MTVSRBM, "mtvsrbm", CONST, vec_mtvsr_v16qi)
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BU_P10V_1 (MTVSRHM, "mtvsrhm", CONST, vec_mtvsr_v8hi)
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BU_P10V_1 (MTVSRWM, "mtvsrwm", CONST, vec_mtvsr_v4si)
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@ -2771,6 +2782,10 @@ BU_P10_OVERLOAD_1 (VSTRIL, "stril")
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BU_P10_OVERLOAD_1 (VSTRIR_P, "strir_p")
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BU_P10_OVERLOAD_1 (VSTRIL_P, "stril_p")
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BU_P10_OVERLOAD_1 (XVTLSBB_ZEROS, "xvtlsbb_all_zeros")
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BU_P10_OVERLOAD_1 (XVTLSBB_ONES, "xvtlsbb_all_ones")
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BU_P10_OVERLOAD_1 (MTVSRBM, "mtvsrbm")
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BU_P10_OVERLOAD_1 (MTVSRHM, "mtvsrhm")
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@ -5681,6 +5681,11 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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{ P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMQ,
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RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, 0, 0 },
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{ P10_BUILTIN_VEC_XVTLSBB_ZEROS, P10_BUILTIN_XVTLSBB_ZEROS,
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RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
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{ P10_BUILTIN_VEC_XVTLSBB_ONES, P10_BUILTIN_XVTLSBB_ONES,
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RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
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{ RS6000_BUILTIN_NONE, RS6000_BUILTIN_NONE, 0, 0, 0, 0 }
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};
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@ -77,6 +77,7 @@
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UNSPEC_TLS_GET_ADDR
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UNSPEC_MOVESI_FROM_CR
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UNSPEC_MOVESI_TO_CR
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UNSPEC_XVTLSBB
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UNSPEC_TLSDTPREL
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UNSPEC_TLSDTPRELHA
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UNSPEC_TLSDTPRELLO
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@ -1985,6 +1985,45 @@
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"xvcmpgt<sd>p. %x0,%x1,%x2"
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[(set_attr "type" "<VStype_simple>")])
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;; xvtlsbb BF,XB
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;; Set the CR field BF to indicate if the lowest bit (bit 7) of every byte
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;; element in VSR[XB] is equal to 1 (ALL_TRUE) or equal to 0 (ALL_FALSE).
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(define_insn "*xvtlsbb_internal"
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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(unspec:CC [(match_operand:V16QI 1 "vsx_register_operand" "wa")]
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UNSPEC_XVTLSBB))]
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"TARGET_POWER10"
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"xvtlsbb %0,%x1"
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[(set_attr "type" "logical")])
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;; Vector Test Least Significant Bit by Byte
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;; for the implementation of the builtin
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;; __builtin_vec_test_lsbb_all_ones
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;; int vec_test_lsbb_all_ones (vector unsigned char);
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;; and
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;; __builtin_vec_test_lsbb_all_zeros
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;; int vec_test_lsbb_all_zeros (vector unsigned char);
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(define_expand "xvtlsbbo"
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[(set (match_dup 2)
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(unspec:CC [(match_operand:V16QI 1 "vsx_register_operand" "v")]
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UNSPEC_XVTLSBB))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(lt:SI (match_dup 2) (const_int 0)))]
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"TARGET_POWER10"
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{
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operands[2] = gen_reg_rtx (CCmode);
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})
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(define_expand "xvtlsbbz"
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[(set (match_dup 2)
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(unspec:CC [(match_operand:V16QI 1 "vsx_register_operand" "v")]
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UNSPEC_XVTLSBB))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(eq:SI (match_dup 2) (const_int 0)))]
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"TARGET_POWER10"
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{
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operands[2] = gen_reg_rtx (CCmode);
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})
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(define_insn "*vsx_ge_<mode>_p"
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[(set (reg:CC CR6_REGNO)
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(unspec:CC
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@ -0,0 +1,65 @@
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/*
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Test the least significant bit by byte instruction
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xvtlsbb BF,XB
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Using the builtins
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int vec_test_lsbb_all_zeros (vector unsigned char);
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int vec_test_lsbb_all_ones (vector unsigned char);
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*/
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/* { dg-do run } */
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/* { dg-require-effective-target power10_hw } */
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/* { dg-options "-fno-inline -mdejagnu-cpu=power10 -O2" } */
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#include <altivec.h>
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#include <stdio.h>
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void abort (void);
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#define ITERS 7
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vector char input_vec[ITERS] = {
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
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{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1},
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{0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1},
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{1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0},
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{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
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{0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe},
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{0xfe, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9}
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};
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int expected_allzeros_results[ITERS] = {1, 0, 0, 0, 0, 1, 0};
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int expected_allones_results[ITERS] = {0, 1, 0, 0, 1, 0, 0};
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int test_for_zeros(vector char vc) {
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return vec_test_lsbb_all_zeros(vc);
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}
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int test_for_ones(vector char vc) {
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return vec_test_lsbb_all_ones(vc);
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}
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int main ()
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{
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int allzeros,allones;
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int iter;
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int failcount=0;
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vector char srcvec;
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for (iter=0;iter<ITERS;iter++) {
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srcvec = input_vec[iter];
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allzeros = test_for_zeros(srcvec);
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allones = test_for_ones(srcvec);
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if (allzeros != expected_allzeros_results[iter]) {
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printf("fail on allzero check. iter %d, result was %d \n", iter, allzeros);
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failcount++;
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}
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if (allones != expected_allones_results[iter]) {
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printf("fail on allones check. iter %d, result was %d \n", iter, allones);
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failcount++;
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}
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}
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if (failcount)
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abort();
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return 0;
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}
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@ -0,0 +1,24 @@
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/*
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Test the least significant bit by byte instruction
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xvtlsbb BF,XB
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Using the builtins
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int vec_test_lsbb_all_zeros (vector unsigned char);
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int vec_test_lsbb_all_ones (vector unsigned char);
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*/
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/* { dg-require-effective-target power10_ok } */
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/* { dg-options "-fno-inline -mdejagnu-cpu=power10 -O2" } */
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/* { dg-final { scan-assembler-times {\mxvtlsbb\M} 2 } } */
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/* { dg-final { scan-assembler-times {\msetbc\M} 2 } } */
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#include <altivec.h>
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int test_for_zeros(vector char vc) {
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return vec_test_lsbb_all_zeros(vc);
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}
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int test_for_ones(vector char vc) {
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return vec_test_lsbb_all_ones(vc);
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}
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