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mips.md (movdicc): Make conditional on TARGET_64BIT.

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* mips.md (movdicc): Make conditional on TARGET_64BIT.  Likewise
	for the unnamed instructions it expands to.

From-SVN: r44568
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Richard Sandiford 2001-08-02 10:27:03 +00:00 committed by Richard Sandiford
parent d3259baad8
commit d6b6ba2921
2 changed files with 9 additions and 4 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2001-08-02 Richard Sandiford <rsandifo@redhat.com>
* mips.md (movdicc): Make conditional on TARGET_64BIT. Likewise
for the unnamed instructions it expands to.
2001-08-02 Richard Henderson <rth@redhat.com> 2001-08-02 Richard Henderson <rth@redhat.com>
* regclass.c (call_really_used_regs): Conditionally define. * regclass.c (call_really_used_regs): Conditionally define.

8
gcc/config/mips/mips.md
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@ -10180,7 +10180,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\;j\\t%2"
(const_int 0)]) (const_int 0)])
(match_operand:DI 2 "se_reg_or_0_operand" "dJ,0") (match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))] (match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
"ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE" "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
"@ "@
mov%B4\\t%0,%z2,%1 mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1" mov%b4\\t%0,%z3,%1"
@ -10195,7 +10195,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\;j\\t%2"
(const_int 0)]) (const_int 0)])
(match_operand:DI 2 "se_reg_or_0_operand" "dJ,0") (match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))] (match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
"ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE" "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
"@ "@
mov%B4\\t%0,%z2,%1 mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1" mov%b4\\t%0,%z3,%1"
@ -10211,7 +10211,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\;j\\t%2"
(const_int 0)]) (const_int 0)])
(match_operand:DI 1 "se_reg_or_0_operand" "dJ,0") (match_operand:DI 1 "se_reg_or_0_operand" "dJ,0")
(match_operand:DI 2 "se_reg_or_0_operand" "0,dJ")))] (match_operand:DI 2 "se_reg_or_0_operand" "0,dJ")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT" "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_64BIT"
"@ "@
mov%T3\\t%0,%z1,%4 mov%T3\\t%0,%z1,%4
mov%t3\\t%0,%z2,%4" mov%t3\\t%0,%z2,%4"
@ -10331,7 +10331,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\;j\\t%2"
(if_then_else:DI (match_dup 5) (if_then_else:DI (match_dup 5)
(match_operand:DI 2 "se_reg_or_0_operand" "") (match_operand:DI 2 "se_reg_or_0_operand" "")
(match_operand:DI 3 "se_reg_or_0_operand" "")))] (match_operand:DI 3 "se_reg_or_0_operand" "")))]
"ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE" "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
" "
{ {
gen_conditional_move (operands); gen_conditional_move (operands);