i386.md (add?i_3, add?i_5): New.
* i386.md (add?i_3, add?i_5): New. (add?i_4): Rename from add?i_3; Fix compare pattern. (sub?i_3, xor?i_3, ior?i_3): New. * genrecog.c (write_tree): Output code to clear insn_extract cache. * genattrtab.c (write_attr_case): Gen call to extract_insn_cache instead of extract_insn and extract_constrain_insn_cache instead of extract_insn and constrain_operands. * recog.c (extract_insn_cached, extract_constrain_insn_cached): New functions. (extract_insn): Clear which_alternative. (constrain_operands): Set which_alternative to -1 when failed. * recog.h (extract_constrain_insn_cached, extract_insn_cached): Declare. From-SVN: r36342
This commit is contained in:
Jan Hubicka
Jan Hubicka
parent
14203c9cac
commit
d90ffc8d2c
@ -1,3 +1,20 @@
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Tue Sep 12 01:51:38 MET DST 2000 Jan Hubicka <jh@suse.cz>
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* i386.md (add?i_3, add?i_5): New.
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(add?i_4): Rename from add?i_3; Fix compare pattern.
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(sub?i_3, xor?i_3, ior?i_3): New.
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* genrecog.c (write_tree): Output code to clear insn_extract cache.
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* genattrtab.c (write_attr_case): Gen call to extract_insn_cache
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instead of extract_insn and extract_constrain_insn_cache instead of
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extract_insn and constrain_operands.
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* recog.c (extract_insn_cached, extract_constrain_insn_cached):
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New functions.
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(extract_insn): Clear which_alternative.
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(constrain_operands): Set which_alternative to -1 when failed.
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* recog.h (extract_constrain_insn_cached, extract_insn_cached):
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Declare.
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2000-09-11 Matthew Hiller <hiller@redhat.com>
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* config/h8300/h8300.md (movstrictqi): Changed constraint modifier
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@ -3997,10 +3997,55 @@
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(set_attr "mode" "SI")])
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(define_insn "*addsi_3"
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[(set (reg 17)
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(compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
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(match_operand:SI 1 "nonimmediate_operand" "%0")))
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(clobber (match_scratch:SI 0 "=r"))]
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"ix86_match_ccmode (insn, CCNOmode)
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&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
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/* Current assemblers are broken and do not allow @GOTOFF in
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ought but a memory context. */
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&& ! pic_symbolic_operand (operands[2], VOIDmode)"
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"*
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{
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switch (get_attr_type (insn))
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{
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case TYPE_INCDEC:
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if (! rtx_equal_p (operands[0], operands[1]))
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abort ();
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if (operands[2] == const1_rtx)
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return \"inc{l}\\t%0\";
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else if (operands[2] == constm1_rtx)
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return \"dec{l}\\t%0\";
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else
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abort();
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default:
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if (! rtx_equal_p (operands[0], operands[1]))
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abort ();
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/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
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Exceptions: -128 encodes smaller than 128, so swap sign and op. */
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if (GET_CODE (operands[2]) == CONST_INT
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&& (INTVAL (operands[2]) == 128
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|| (INTVAL (operands[2]) < 0
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&& INTVAL (operands[2]) != -128)))
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{
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operands[2] = GEN_INT (-INTVAL (operands[2]));
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return \"sub{l}\\t{%2, %0|%0, %2}\";
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}
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return \"add{l}\\t{%2, %0|%0, %2}\";
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}
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}"
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[(set (attr "type")
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(if_then_else (match_operand:SI 2 "incdec_operand" "")
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(const_string "incdec")
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(const_string "alu")))
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(set_attr "mode" "SI")])
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(define_insn "*addsi_4"
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[(set (reg:CC 17)
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(compare:CC (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
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(match_operand:SI 2 "general_operand" "rmni,rni"))
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(const_int 0)))
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(compare:CC (neg:SI (match_operand:SI 2 "general_operand" "rmni,rni"))
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(match_operand:SI 1 "nonimmediate_operand" "%0,0")))
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(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
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(plus:SI (match_dup 1) (match_dup 2)))]
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"ix86_binary_operator_ok (PLUS, SImode, operands)
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@ -4011,6 +4056,19 @@
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[(set_attr "type" "alu")
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(set_attr "mode" "SI")])
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(define_insn "*addsi_5"
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[(set (reg:CC 17)
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(compare:CC (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
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(match_operand:SI 1 "nonimmediate_operand" "%0")))
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(clobber (match_scratch:SI 0 "=r"))]
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"(GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
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/* Current assemblers are broken and do not allow @GOTOFF in
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ought but a memory context. */
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&& ! pic_symbolic_operand (operands[2], VOIDmode)"
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"add{l}\\t{%2, %0|%0, %2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "SI")])
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(define_expand "addhi3"
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[(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
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(plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
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@ -4151,10 +4209,49 @@
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(set_attr "mode" "HI")])
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(define_insn "*addhi_3"
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[(set (reg 17)
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(compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
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(match_operand:HI 1 "nonimmediate_operand" "%0")))
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(clobber (match_scratch:HI 0 "=r"))]
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"ix86_match_ccmode (insn, CCNOmode)
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&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
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"*
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{
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switch (get_attr_type (insn))
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{
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case TYPE_INCDEC:
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if (operands[2] == const1_rtx)
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return \"inc{w}\\t%0\";
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else if (operands[2] == constm1_rtx
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|| (GET_CODE (operands[2]) == CONST_INT
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&& INTVAL (operands[2]) == 65535))
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return \"dec{w}\\t%0\";
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abort();
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default:
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/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
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Exceptions: -128 encodes smaller than 128, so swap sign and op. */
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if (GET_CODE (operands[2]) == CONST_INT
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&& (INTVAL (operands[2]) == 128
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|| (INTVAL (operands[2]) < 0
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&& INTVAL (operands[2]) != -128)))
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{
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operands[2] = GEN_INT (-INTVAL (operands[2]));
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return \"sub{w}\\t{%2, %0|%0, %2}\";
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}
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return \"add{w}\\t{%2, %0|%0, %2}\";
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}
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}"
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[(set (attr "type")
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(if_then_else (match_operand:HI 2 "incdec_operand" "")
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(const_string "incdec")
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(const_string "alu")))
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(set_attr "mode" "HI")])
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(define_insn "*addhi_4"
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[(set (reg:CC 17)
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(compare:CC (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
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(match_operand:HI 2 "general_operand" "rmni,rni"))
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(const_int 0)))
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(compare:CC (neg:HI (match_operand:HI 2 "general_operand" "rmni,rni"))
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(match_operand:HI 1 "nonimmediate_operand" "%0,0")))
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(set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
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(plus:HI (match_dup 1) (match_dup 2)))]
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"ix86_binary_operator_ok (PLUS, HImode, operands)"
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@ -4162,6 +4259,16 @@
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[(set_attr "type" "alu")
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(set_attr "mode" "HI")])
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(define_insn "*addhi_5"
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[(set (reg:CC 17)
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(compare:CC (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
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(match_operand:HI 1 "nonimmediate_operand" "%0")))
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(clobber (match_scratch:HI 0 "=r"))]
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"(GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
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"add{w}\\t{%2, %0|%0, %2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "HI")])
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(define_expand "addqi3"
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[(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
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(plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
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@ -4310,10 +4417,46 @@
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(set_attr "mode" "QI")])
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(define_insn "*addqi_3"
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[(set (reg 17)
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(compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
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(match_operand:QI 1 "nonimmediate_operand" "%0")))
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(clobber (match_scratch:QI 0 "=r"))]
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"ix86_match_ccmode (insn, CCNOmode)
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&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
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"*
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{
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switch (get_attr_type (insn))
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{
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case TYPE_INCDEC:
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if (operands[2] == const1_rtx)
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return \"inc{b}\\t%0\";
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else if (operands[2] == constm1_rtx
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|| (GET_CODE (operands[2]) == CONST_INT
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&& INTVAL (operands[2]) == 255))
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return \"dec{b}\\t%0\";
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abort();
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default:
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/* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
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if (GET_CODE (operands[2]) == CONST_INT
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&& INTVAL (operands[2]) < 0)
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{
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operands[2] = GEN_INT (-INTVAL (operands[2]));
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return \"sub{b}\\t{%2, %0|%0, %2}\";
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}
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return \"add{b}\\t{%2, %0|%0, %2}\";
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}
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}"
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[(set (attr "type")
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(if_then_else (match_operand:QI 2 "incdec_operand" "")
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(const_string "incdec")
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(const_string "alu")))
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(set_attr "mode" "QI")])
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(define_insn "*addqi_4"
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[(set (reg:CC 17)
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(compare:CC (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
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(match_operand:QI 2 "general_operand" "qmni,qni"))
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(const_int 0)))
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(compare:CC (neg:QI (match_operand:QI 2 "general_operand" "qmni,qni"))
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(match_operand:QI 1 "nonimmediate_operand" "%0,0")))
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(set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
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(plus:QI (match_dup 1) (match_dup 2)))]
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"ix86_binary_operator_ok (PLUS, QImode, operands)"
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@ -4321,6 +4464,16 @@
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[(set_attr "type" "alu")
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(set_attr "mode" "QI")])
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(define_insn "*addqi_5"
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[(set (reg:CC 17)
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(compare:CC (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
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(match_operand:QI 1 "nonimmediate_operand" "%0")))
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(clobber (match_scratch:QI 0 "=r"))]
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"(GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
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"add{b}\\t{%2, %0|%0, %2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "QI")])
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(define_insn "addqi_ext_1"
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[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
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@ -4478,6 +4631,18 @@
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(const_int 0)))
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(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
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(minus:SI (match_dup 1) (match_dup 2)))]
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"ix86_match_ccmode (insn, CCNOmode)
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&& ix86_binary_operator_ok (MINUS, SImode, operands)"
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"sub{l}\\t{%2, %0|%0, %2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "SI")])
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(define_insn "*subsi_3"
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[(set (reg 17)
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(compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
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(match_operand:SI 2 "general_operand" "ri,rm")))
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(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
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(minus:SI (match_dup 1) (match_dup 2)))]
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"ix86_match_ccmode (insn, CCmode)
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&& ix86_binary_operator_ok (MINUS, SImode, operands)"
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"sub{l}\\t{%2, %0|%0, %2}"
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@ -4510,6 +4675,18 @@
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(const_int 0)))
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(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
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(minus:HI (match_dup 1) (match_dup 2)))]
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"ix86_match_ccmode (insn, CCNOmode)
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&& ix86_binary_operator_ok (MINUS, HImode, operands)"
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"sub{w}\\t{%2, %0|%0, %2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "HI")])
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(define_insn "*subhi_3"
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[(set (reg 17)
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(compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
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(match_operand:HI 2 "general_operand" "ri,rm")))
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(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
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(minus:HI (match_dup 1) (match_dup 2)))]
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"ix86_match_ccmode (insn, CCmode)
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&& ix86_binary_operator_ok (MINUS, HImode, operands)"
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"sub{w}\\t{%2, %0|%0, %2}"
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@ -4542,6 +4719,18 @@
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(const_int 0)))
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(set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
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(minus:HI (match_dup 1) (match_dup 2)))]
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"ix86_match_ccmode (insn, CCNOmode)
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&& ix86_binary_operator_ok (MINUS, QImode, operands)"
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"sub{b}\\t{%2, %0|%0, %2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "QI")])
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(define_insn "*subqi_3"
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[(set (reg 17)
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(compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
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(match_operand:QI 2 "general_operand" "qi,qm")))
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(set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
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(minus:HI (match_dup 1) (match_dup 2)))]
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"ix86_match_ccmode (insn, CCmode)
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&& ix86_binary_operator_ok (MINUS, QImode, operands)"
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"sub{b}\\t{%2, %0|%0, %2}"
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@ -5491,6 +5680,18 @@
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[(set_attr "type" "alu")
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(set_attr "mode" "SI")])
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(define_insn "*iorsi_3"
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[(set (reg 17)
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(compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
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(match_operand:SI 2 "general_operand" "rim"))
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(const_int 0)))
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(clobber (match_scratch:SI 0 "=r"))]
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"ix86_match_ccmode (insn, CCNOmode)
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&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
|
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"or{l}\\t{%2, %0|%0, %2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "SI")])
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(define_expand "iorhi3"
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[(set (match_operand:HI 0 "nonimmediate_operand" "")
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(ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
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@ -5522,6 +5723,18 @@
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[(set_attr "type" "alu")
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(set_attr "mode" "HI")])
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(define_insn "*iorhi_3"
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[(set (reg 17)
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(compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
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(match_operand:HI 2 "general_operand" "rim"))
|
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(const_int 0)))
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(clobber (match_scratch:HI 0 "=r"))]
|
||||
"ix86_match_ccmode (insn, CCNOmode)
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&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
|
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"or{w}\\t{%2, %0|%0, %2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "HI")])
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|
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(define_expand "iorqi3"
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[(set (match_operand:QI 0 "nonimmediate_operand" "")
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(ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
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@ -5556,6 +5769,19 @@
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"or{b}\\t{%2, %0|%0, %2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "QI")])
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|
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(define_insn "*iorqi_3"
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[(set (reg 17)
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(compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
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(match_operand:QI 2 "general_operand" "qim"))
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(const_int 0)))
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(clobber (match_scratch:QI 0 "=r"))]
|
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"ix86_match_ccmode (insn, CCNOmode)
|
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&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
|
||||
"or{b}\\t{%2, %0|%0, %2}"
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[(set_attr "type" "alu")
|
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(set_attr "mode" "QI")])
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|
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;; Logical XOR instructions
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||||
@ -5593,6 +5819,18 @@
|
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[(set_attr "type" "alu")
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(set_attr "mode" "SI")])
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|
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(define_insn "*xorsi_3"
|
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[(set (reg 17)
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(compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
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||||
(match_operand:SI 2 "general_operand" "rim"))
|
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(const_int 0)))
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(clobber (match_scratch:SI 0 "=r"))]
|
||||
"ix86_match_ccmode (insn, CCNOmode)
|
||||
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
|
||||
"xor{l}\\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "alu")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_expand "xorhi3"
|
||||
[(set (match_operand:HI 0 "nonimmediate_operand" "")
|
||||
(xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
|
||||
@ -5624,6 +5862,18 @@
|
||||
[(set_attr "type" "alu")
|
||||
(set_attr "mode" "HI")])
|
||||
|
||||
(define_insn "*xorhi_3"
|
||||
[(set (reg 17)
|
||||
(compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
|
||||
(match_operand:HI 2 "general_operand" "rim"))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:HI 0 "=r"))]
|
||||
"ix86_match_ccmode (insn, CCNOmode)
|
||||
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
|
||||
"xor{w}\\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "alu")
|
||||
(set_attr "mode" "HI")])
|
||||
|
||||
(define_expand "xorqi3"
|
||||
[(set (match_operand:QI 0 "nonimmediate_operand" "")
|
||||
(xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
|
||||
@ -5678,6 +5928,19 @@
|
||||
[(set_attr "type" "alu")
|
||||
(set_attr "mode" "QI")])
|
||||
|
||||
(define_insn "*xorqi_cc_2"
|
||||
[(set (reg 17)
|
||||
(compare
|
||||
(xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
|
||||
(match_operand:QI 2 "general_operand" "qim"))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:QI 0 "=r"))]
|
||||
"ix86_match_ccmode (insn, CCNOmode)
|
||||
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
|
||||
"xor{b}\\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "alu")
|
||||
(set_attr "mode" "QI")])
|
||||
|
||||
(define_insn "xorqi_cc_ext_1"
|
||||
[(set (reg:CCNO 17)
|
||||
(compare:CCNO
|
||||
|
||||
@ -5212,18 +5212,15 @@ write_attr_case (attr, av, write_case_lines, prefix, suffix, indent,
|
||||
must_extract = must_constrain = address_used = 0;
|
||||
walk_attr_value (av->value);
|
||||
|
||||
if (must_extract)
|
||||
{
|
||||
write_indent (indent + 2);
|
||||
printf ("extract_insn (insn);\n");
|
||||
}
|
||||
|
||||
if (must_constrain)
|
||||
{
|
||||
write_indent (indent + 2);
|
||||
printf ("if (! constrain_operands (reload_completed))\n");
|
||||
printf ("extract_constrain_insn_cached (insn);\n");
|
||||
}
|
||||
else if (must_extract)
|
||||
{
|
||||
write_indent (indent + 2);
|
||||
printf (" fatal_insn_not_found (insn);\n");
|
||||
printf ("extract_insn_cached (insn);\n");
|
||||
}
|
||||
|
||||
write_attr_set (attr, indent + 2, av->value, prefix, suffix,
|
||||
|
||||
@ -2189,6 +2189,9 @@ peephole2%s (x0, insn, _pmatch_len)\n\
|
||||
|
||||
printf (" %s tem ATTRIBUTE_UNUSED;\n", IS_SPLIT (type) ? "rtx" : "int");
|
||||
|
||||
if (!subfunction)
|
||||
printf (" recog_data.insn = NULL_RTX;\n");
|
||||
|
||||
if (head->first)
|
||||
write_tree (head, "", type, 1);
|
||||
else
|
||||
|
||||
28
gcc/recog.c
28
gcc/recog.c
@ -2045,6 +2045,31 @@ adj_offsettable_operand (op, offset)
|
||||
abort ();
|
||||
}
|
||||
|
||||
/* Like extract_insn, but save insn extracted and don't extract again, when
|
||||
called again for the same insn expecting that recog_data still contain the
|
||||
valid information. This is used primary by gen_attr infrastructure that
|
||||
often does extract insn again and again. */
|
||||
void
|
||||
extract_insn_cached (insn)
|
||||
rtx insn;
|
||||
{
|
||||
if (recog_data.insn == insn && INSN_CODE (insn) >= 0)
|
||||
return;
|
||||
extract_insn (insn);
|
||||
recog_data.insn = insn;
|
||||
}
|
||||
/* Do cached extract_insn, constrain_operand and complain about failures.
|
||||
Used by insn_attrtab. */
|
||||
void
|
||||
extract_constrain_insn_cached (insn)
|
||||
rtx insn;
|
||||
{
|
||||
extract_insn_cached (insn);
|
||||
if (which_alternative == -1
|
||||
&& !constrain_operands (reload_completed))
|
||||
fatal_insn_not_found (insn);
|
||||
}
|
||||
|
||||
/* Analyze INSN and fill in recog_data. */
|
||||
|
||||
void
|
||||
@ -2056,9 +2081,11 @@ extract_insn (insn)
|
||||
int noperands;
|
||||
rtx body = PATTERN (insn);
|
||||
|
||||
recog_data.insn = NULL;
|
||||
recog_data.n_operands = 0;
|
||||
recog_data.n_alternatives = 0;
|
||||
recog_data.n_dups = 0;
|
||||
which_alternative = -1;
|
||||
|
||||
switch (GET_CODE (body))
|
||||
{
|
||||
@ -2592,6 +2619,7 @@ constrain_operands (strict)
|
||||
which_alternative++;
|
||||
}
|
||||
|
||||
which_alternative = -1;
|
||||
/* If we are about to reject this, but we are not to test strictly,
|
||||
try a very loose test. Only return failure if it fails also. */
|
||||
if (strict == 0)
|
||||
|
||||
@ -116,6 +116,8 @@ extern int recog PARAMS ((rtx, rtx, int *));
|
||||
extern void add_clobbers PARAMS ((rtx, int));
|
||||
extern void insn_extract PARAMS ((rtx));
|
||||
extern void extract_insn PARAMS ((rtx));
|
||||
extern void extract_constrain_insn_cached PARAMS ((rtx));
|
||||
extern void extract_insn_cached PARAMS ((rtx));
|
||||
extern void preprocess_constraints PARAMS ((void));
|
||||
extern rtx peep2_next_insn PARAMS ((int));
|
||||
extern int peep2_regno_dead_p PARAMS ((int, int));
|
||||
@ -186,6 +188,9 @@ struct recog_data
|
||||
|
||||
/* The number of alternatives in the constraints for the insn. */
|
||||
char n_alternatives;
|
||||
|
||||
/* In case we are caching, hold insn data was generated for. */
|
||||
rtx insn;
|
||||
};
|
||||
|
||||
extern struct recog_data recog_data;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user