mips.md (*baddu_si_eb, [...]): Merge into...
gcc/ * config/mips/mips.md (*baddu_si_eb, *baddu_si_el): Merge into... (*baddu_si): ...this new pattern. From-SVN: r191997
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2012-10-02 Richard Sandiford <rdsandiford@googlemail.com>
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* config/mips/mips.md (*baddu_si_eb, *baddu_si_el): Merge into...
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(*baddu_si): ...this new pattern.
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2012-10-02 Richard Sandiford <rdsandiford@googlemail.com>
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2012-10-02 Richard Sandiford <rdsandiford@googlemail.com>
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* ira-int.h (target_ira_int): Add x_ira_useful_class_mode_regs.
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* ira-int.h (target_ira_int): Add x_ira_useful_class_mode_regs.
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@ -1293,23 +1293,12 @@
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;; Combiner patterns for unsigned byte-add.
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;; Combiner patterns for unsigned byte-add.
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(define_insn "*baddu_si_eb"
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(define_insn "*baddu_si"
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[(set (match_operand:SI 0 "register_operand" "=d")
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[(set (match_operand:SI 0 "register_operand" "=d")
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(zero_extend:SI
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(zero_extend:SI
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(subreg:QI
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(plus:QI (match_operand:QI 1 "register_operand" "d")
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(plus:SI (match_operand:SI 1 "register_operand" "d")
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(match_operand:QI 2 "register_operand" "d"))))]
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(match_operand:SI 2 "register_operand" "d")) 3)))]
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"ISA_HAS_BADDU"
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"ISA_HAS_BADDU && BYTES_BIG_ENDIAN"
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"baddu\\t%0,%1,%2"
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[(set_attr "alu_type" "add")])
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(define_insn "*baddu_si_el"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(zero_extend:SI
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(subreg:QI
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(plus:SI (match_operand:SI 1 "register_operand" "d")
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(match_operand:SI 2 "register_operand" "d")) 0)))]
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"ISA_HAS_BADDU && !BYTES_BIG_ENDIAN"
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"baddu\\t%0,%1,%2"
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"baddu\\t%0,%1,%2"
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[(set_attr "alu_type" "add")])
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[(set_attr "alu_type" "add")])
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