re PR target/88461 (AVX512: gcc should keep value in kN registers if possible)
PR target/88461 * config/i386/sse.md (VI1248_AVX512VLBW, AVX512ZEXTMASK): New mode iterators. (<avx512>_testm<mode>3<mask_scalar_merge_name>, <avx512>_testnm<mode>3<mask_scalar_merge_name>): Merge patterns with VI12_AVX512VL and VI48_AVX512VL iterators into ones with VI1248_AVX512VLBW iterator. (*<avx512>_testm<VI1248_AVX512VLBW:mode>3_zext, *<avx512>_testm<VI1248_AVX512VLBW:mode>3_zext_mask, *<avx512>_testnm<VI1248_AVX512VLBW:mode>3_zext, *<avx512>_testnm<VI1248_AVX512VLBW:mode>3_zext_mask): New define_insns. * gcc.target/i386/pr88461.c: New test. From-SVN: r267077
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Jakub Jelinek
Jakub Jelinek
parent
87d570a022
commit
e00199d7b7
@ -1,5 +1,18 @@
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2018-12-13 Jakub Jelinek <jakub@redhat.com>
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PR target/88461
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* config/i386/sse.md (VI1248_AVX512VLBW, AVX512ZEXTMASK): New
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mode iterators.
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(<avx512>_testm<mode>3<mask_scalar_merge_name>,
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<avx512>_testnm<mode>3<mask_scalar_merge_name>): Merge patterns
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with VI12_AVX512VL and VI48_AVX512VL iterators into ones with
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VI1248_AVX512VLBW iterator.
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(*<avx512>_testm<VI1248_AVX512VLBW:mode>3_zext,
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*<avx512>_testm<VI1248_AVX512VLBW:mode>3_zext_mask,
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*<avx512>_testnm<VI1248_AVX512VLBW:mode>3_zext,
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*<avx512>_testnm<VI1248_AVX512VLBW:mode>3_zext_mask): New
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define_insns.
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PR target/88461
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* config/i386/i386.md (*zero_extendsidi2, zero_extend<mode>di2,
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*zero_extend<mode>si2, *zero_extendqihi2): Add =*k, *km alternatives.
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@ -12322,22 +12322,22 @@
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(set_attr "prefix" "evex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn "<avx512>_testm<mode>3<mask_scalar_merge_name>"
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[(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
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(unspec:<avx512fmaskmode>
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[(match_operand:VI12_AVX512VL 1 "register_operand" "v")
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(match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")]
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UNSPEC_TESTM))]
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"TARGET_AVX512BW"
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"vptestm<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
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[(set_attr "prefix" "evex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_mode_iterator VI1248_AVX512VLBW
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[(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX512VL && TARGET_AVX512BW")
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(V16QI "TARGET_AVX512VL && TARGET_AVX512BW")
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(V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX512VL && TARGET_AVX512BW")
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(V8HI "TARGET_AVX512VL && TARGET_AVX512BW")
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V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL")
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V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")])
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(define_mode_iterator AVX512ZEXTMASK
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[(DI "TARGET_AVX512BW") (SI "TARGET_AVX512BW") HI])
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(define_insn "<avx512>_testm<mode>3<mask_scalar_merge_name>"
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[(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
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(unspec:<avx512fmaskmode>
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[(match_operand:VI48_AVX512VL 1 "register_operand" "v")
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(match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")]
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[(match_operand:VI1248_AVX512VLBW 1 "register_operand" "v")
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(match_operand:VI1248_AVX512VLBW 2 "nonimmediate_operand" "vm")]
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UNSPEC_TESTM))]
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"TARGET_AVX512F"
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"vptestm<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
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@ -12347,25 +12347,74 @@
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(define_insn "<avx512>_testnm<mode>3<mask_scalar_merge_name>"
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[(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
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(unspec:<avx512fmaskmode>
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[(match_operand:VI12_AVX512VL 1 "register_operand" "v")
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(match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")]
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UNSPEC_TESTNM))]
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"TARGET_AVX512BW"
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"vptestnm<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
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[(set_attr "prefix" "evex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn "<avx512>_testnm<mode>3<mask_scalar_merge_name>"
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[(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
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(unspec:<avx512fmaskmode>
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[(match_operand:VI48_AVX512VL 1 "register_operand" "v")
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(match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")]
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[(match_operand:VI1248_AVX512VLBW 1 "register_operand" "v")
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(match_operand:VI1248_AVX512VLBW 2 "nonimmediate_operand" "vm")]
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UNSPEC_TESTNM))]
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"TARGET_AVX512F"
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"vptestnm<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
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[(set_attr "prefix" "evex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn "*<avx512>_testm<VI1248_AVX512VLBW:mode>3_zext"
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[(set (match_operand:AVX512ZEXTMASK 0 "register_operand" "=Yk")
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(zero_extend:AVX512ZEXTMASK
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(unspec:<VI1248_AVX512VLBW:avx512fmaskmode>
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[(match_operand:VI1248_AVX512VLBW 1 "register_operand" "v")
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(match_operand:VI1248_AVX512VLBW 2 "nonimmediate_operand" "vm")]
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UNSPEC_TESTM)))]
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"TARGET_AVX512BW
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&& (<AVX512ZEXTMASK:MODE_SIZE>
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> GET_MODE_SIZE (<VI1248_AVX512VLBW:avx512fmaskmode>mode))"
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"vptestm<VI1248_AVX512VLBW:ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "prefix" "evex")
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(set_attr "mode" "<VI1248_AVX512VLBW:sseinsnmode>")])
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(define_insn "*<avx512>_testm<VI1248_AVX512VLBW:mode>3_zext_mask"
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[(set (match_operand:AVX512ZEXTMASK 0 "register_operand" "=Yk")
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(zero_extend:AVX512ZEXTMASK
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(and:<VI1248_AVX512VLBW:avx512fmaskmode>
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(unspec:<VI1248_AVX512VLBW:avx512fmaskmode>
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[(match_operand:VI1248_AVX512VLBW 1 "register_operand" "v")
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(match_operand:VI1248_AVX512VLBW 2 "nonimmediate_operand" "vm")]
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UNSPEC_TESTM)
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(match_operand:<VI1248_AVX512VLBW:avx512fmaskmode> 3 "register_operand" "Yk"))))]
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"TARGET_AVX512BW
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&& (<AVX512ZEXTMASK:MODE_SIZE>
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> GET_MODE_SIZE (<VI1248_AVX512VLBW:avx512fmaskmode>mode))"
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"vptestm<VI1248_AVX512VLBW:ssemodesuffix>\t{%2, %1, %0%{%3%}|%0%{%3%}, %1, %2}"
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[(set_attr "prefix" "evex")
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(set_attr "mode" "<VI1248_AVX512VLBW:sseinsnmode>")])
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(define_insn "*<avx512>_testnm<VI1248_AVX512VLBW:mode>3_zext"
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[(set (match_operand:AVX512ZEXTMASK 0 "register_operand" "=Yk")
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(zero_extend:AVX512ZEXTMASK
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(unspec:<VI1248_AVX512VLBW:avx512fmaskmode>
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[(match_operand:VI1248_AVX512VLBW 1 "register_operand" "v")
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(match_operand:VI1248_AVX512VLBW 2 "nonimmediate_operand" "vm")]
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UNSPEC_TESTNM)))]
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"TARGET_AVX512BW
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&& (<AVX512ZEXTMASK:MODE_SIZE>
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> GET_MODE_SIZE (<VI1248_AVX512VLBW:avx512fmaskmode>mode))"
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"vptestnm<VI1248_AVX512VLBW:ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "prefix" "evex")
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(set_attr "mode" "<VI1248_AVX512VLBW:sseinsnmode>")])
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(define_insn "*<avx512>_testnm<VI1248_AVX512VLBW:mode>3_zext_mask"
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[(set (match_operand:AVX512ZEXTMASK 0 "register_operand" "=Yk")
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(zero_extend:AVX512ZEXTMASK
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(and:<VI1248_AVX512VLBW:avx512fmaskmode>
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(unspec:<VI1248_AVX512VLBW:avx512fmaskmode>
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[(match_operand:VI1248_AVX512VLBW 1 "register_operand" "v")
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(match_operand:VI1248_AVX512VLBW 2 "nonimmediate_operand" "vm")]
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UNSPEC_TESTNM)
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(match_operand:<VI1248_AVX512VLBW:avx512fmaskmode> 3 "register_operand" "Yk"))))]
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"TARGET_AVX512BW
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&& (<AVX512ZEXTMASK:MODE_SIZE>
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> GET_MODE_SIZE (<VI1248_AVX512VLBW:avx512fmaskmode>mode))"
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"vptestnm<VI1248_AVX512VLBW:ssemodesuffix>\t{%2, %1, %0%{%3%}|%0%{%3%}, %1, %2}"
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[(set_attr "prefix" "evex")
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(set_attr "mode" "<VI1248_AVX512VLBW:sseinsnmode>")])
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Parallel integral element swizzling
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@ -1,3 +1,8 @@
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2018-12-13 Jakub Jelinek <jakub@redhat.com>
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PR target/88461
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* gcc.target/i386/pr88461.c: New test.
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2018-12-12 Paolo Carlini <paolo.carlini@oracle.com>
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* g++.dg/other/static5.C: New.
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16
gcc/testsuite/gcc.target/i386/pr88461.c
Normal file
16
gcc/testsuite/gcc.target/i386/pr88461.c
Normal file
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/* PR target/88461 */
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/* { dg-do compile } */
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/* { dg-options "-O2 -mavx512vl -mavx512bw" } */
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/* { dg-final { scan-assembler-times "kmovw\[ \t]" 2 } } */
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#include <x86intrin.h>
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int
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foo (const __m128i *data, int a)
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{
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__m128i v = _mm_load_si128 (data);
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__mmask16 m = _mm_testn_epi16_mask (v, v);
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m = _kshiftli_mask16 (m, 1);
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m = _kandn_mask16 (m, a);
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return m;
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}
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