mips.md: Add back scheduling exclusion info.
2004-06-25 Eric Christopher <echristo@redhat.com> * config/mips/mips.md: Add back scheduling exclusion info. From-SVN: r83699
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2004-06-25 Eric Christopher <echristo@redhat.com>
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* config/mips/mips.md: Add back scheduling exclusion info.
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2004-06-25 Roger Sayle <roger@eyesopen.com>
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2004-06-25 Roger Sayle <roger@eyesopen.com>
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* ifcvt.c (seq_contains_jump): Delete function.
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* ifcvt.c (seq_contains_jump): Delete function.
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@ -10,7 +14,7 @@
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PR wrong-code/15089
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PR wrong-code/15089
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* loop.c (scan_loop): Do not move user-specified register
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* loop.c (scan_loop): Do not move user-specified register
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assignments.
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assignments.
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2004-06-25 DJ Delorie <dj@redhat.com>
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2004-06-25 DJ Delorie <dj@redhat.com>
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* c-common.h (warn_cast_qual, warn_missing_format_attribute,
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* c-common.h (warn_cast_qual, warn_missing_format_attribute,
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@ -98,7 +102,7 @@
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2004-06-25 Devang Patel <dpatel@apple.com>
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2004-06-25 Devang Patel <dpatel@apple.com>
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* doc/tree-ssa.texi: Document info about MODIFY_EXPR's type
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* doc/tree-ssa.texi: Document info about MODIFY_EXPR's type
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2004-06-25 Paul Brook <paul@codesourcery.com>
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2004-06-25 Paul Brook <paul@codesourcery.com>
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* target-def.h (TARGET_CXX_GUARD_TYPE, TARGET_CXX_GUARD_MASK_BIT,
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* target-def.h (TARGET_CXX_GUARD_TYPE, TARGET_CXX_GUARD_MASK_BIT,
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@ -114,10 +118,10 @@
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TARGET_CXX_GUARD_MASK_BIT.
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TARGET_CXX_GUARD_MASK_BIT.
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2004-06-25 Devang Patel <dpatel@apple.com>
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2004-06-25 Devang Patel <dpatel@apple.com>
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* config/rs6000/darwin.h (CC1_SPEC): Handle -gused and -gfull.
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* config/rs6000/darwin.h (CC1_SPEC): Handle -gused and -gfull.
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* config/i386/darwin.h (CC1_SPEC): Same.
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* config/i386/darwin.h (CC1_SPEC): Same.
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2004-06-25 Mark G. Adams <mark.g.adams@sympatico.ca>
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2004-06-25 Mark G. Adams <mark.g.adams@sympatico.ca>
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* dbxout.h: Add include guards
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* dbxout.h: Add include guards
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@ -141,7 +145,7 @@
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on armv5.
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on armv5.
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* arm.h (arm_arch4t): Declare.
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* arm.h (arm_arch4t): Declare.
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* arm.md (call_reg_armv5, call_value_reg_armv5): New.
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* arm.md (call_reg_armv5, call_value_reg_armv5): New.
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(call_reg_arm, call_value_reg_arm): Renamed from call_reg and
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(call_reg_arm, call_value_reg_arm): Renamed from call_reg and
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call_value_reg respectively.
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call_value_reg respectively.
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(call_reg_thumb_v5, call_value_reg_thumb_v5): New.
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(call_reg_thumb_v5, call_value_reg_thumb_v5): New.
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(call_reg_thumb, call_value_reg_thumb): Renamed from call_indirect
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(call_reg_thumb, call_value_reg_thumb): Renamed from call_indirect
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@ -169,7 +173,7 @@
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* gimplify.c (internal_get_tmp_var, gimplify_return_expr): Likewise.
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* gimplify.c (internal_get_tmp_var, gimplify_return_expr): Likewise.
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(gimplify_loop_expr, gimplify_init_constructor): Likewise.
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(gimplify_loop_expr, gimplify_init_constructor): Likewise.
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(gimplify_self_mod_expr, gimplify_cond_expr): Likewise.
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(gimplify_self_mod_expr, gimplify_cond_expr): Likewise.
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PR/16131
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PR/16131
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* gimplify.c (voidify_wrapper_expr): Allow TARGET_EXPR.
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* gimplify.c (voidify_wrapper_expr): Allow TARGET_EXPR.
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@ -326,7 +326,7 @@
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(define_function_unit "memory" 1 0
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(define_function_unit "memory" 1 0
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(and (eq_attr "type" "load,fpload,fpidxload")
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(and (eq_attr "type" "load,fpload,fpidxload")
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(eq_attr "cpu" "r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
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(eq_attr "cpu" "!r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
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3 0)
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3 0)
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(define_function_unit "memory" 1 0
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(define_function_unit "memory" 1 0
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@ -346,7 +346,7 @@
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(define_function_unit "imuldiv" 1 0
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "imul,imadd")
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(and (eq_attr "type" "imul,imadd")
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(eq_attr "cpu" "r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000"))
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(eq_attr "cpu" "!r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000"))
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17 17)
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17 17)
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;; On them mips16, we want to stronly discourage a mult from appearing
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;; On them mips16, we want to stronly discourage a mult from appearing
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@ -398,7 +398,7 @@
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(define_function_unit "imuldiv" 1 0
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "idiv")
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000"))
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(eq_attr "cpu" "!r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000"))
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38 38)
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38 38)
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(define_function_unit "imuldiv" 1 0
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(define_function_unit "imuldiv" 1 0
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;; instructions to be processed in the "imuldiv" unit.
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;; instructions to be processed in the "imuldiv" unit.
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(define_function_unit "adder" 1 1
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(define_function_unit "adder" 1 1
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(and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3900,r6000,r4300,r5000"))
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(and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3900,r6000,r4300,r5000"))
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3 0)
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3 0)
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(define_function_unit "adder" 1 1
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(define_function_unit "adder" 1 1
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1 0)
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1 0)
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(define_function_unit "adder" 1 1
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(define_function_unit "adder" 1 1
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(and (eq_attr "type" "fadd") (eq_attr "cpu" "r3900,r6000,r4300"))
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(and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3900,r6000,r4300"))
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4 0)
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4 0)
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(define_function_unit "adder" 1 1
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(define_function_unit "adder" 1 1
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(define_function_unit "adder" 1 1
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(define_function_unit "adder" 1 1
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(and (eq_attr "type" "fabs,fneg,fmove")
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(and (eq_attr "type" "fabs,fneg,fmove")
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(eq_attr "cpu" "r3900,r4600,r4650,r4300,r5000"))
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(eq_attr "cpu" "!r3900,r4600,r4650,r4300,r5000"))
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2 0)
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2 0)
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(define_function_unit "adder" 1 1
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(define_function_unit "adder" 1 1
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(define_function_unit "mult" 1 1
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(define_function_unit "mult" 1 1
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(and (eq_attr "type" "fmul")
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(and (eq_attr "type" "fmul")
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(and (eq_attr "mode" "SF")
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(and (eq_attr "mode" "SF")
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(eq_attr "cpu" "r3900,r6000,r4600,r4650,r4300,r5000")))
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(eq_attr "cpu" "!r3900,r6000,r4600,r4650,r4300,r5000")))
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7 0)
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7 0)
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(define_function_unit "mult" 1 1
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(define_function_unit "mult" 1 1
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(define_function_unit "mult" 1 1
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(define_function_unit "mult" 1 1
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(and (eq_attr "type" "fmul")
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(and (eq_attr "type" "fmul")
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(and (eq_attr "mode" "DF") (eq_attr "cpu" "r3900,r6000,r4300,r5000")))
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(and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3900,r6000,r4300,r5000")))
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8 0)
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8 0)
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(define_function_unit "mult" 1 1
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(define_function_unit "mult" 1 1
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(define_function_unit "divide" 1 1
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(define_function_unit "divide" 1 1
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(and (eq_attr "type" "fdiv")
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(and (eq_attr "type" "fdiv")
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(and (eq_attr "mode" "SF")
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(and (eq_attr "mode" "SF")
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(eq_attr "cpu" "r3900,r6000,r4600,r4650,r4300,r5000")))
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(eq_attr "cpu" "!r3900,r6000,r4600,r4650,r4300,r5000")))
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23 0)
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23 0)
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(define_function_unit "divide" 1 1
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(define_function_unit "divide" 1 1
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(define_function_unit "divide" 1 1
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(define_function_unit "divide" 1 1
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(and (eq_attr "type" "fdiv")
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(and (eq_attr "type" "fdiv")
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(and (eq_attr "mode" "DF")
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(and (eq_attr "mode" "DF")
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(eq_attr "cpu" "r3900,r6000,r4600,r4650,r4300")))
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(eq_attr "cpu" "!r3900,r6000,r4600,r4650,r4300")))
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36 0)
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36 0)
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(define_function_unit "divide" 1 1
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(define_function_unit "divide" 1 1
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