mips.md (mfhilo_[sd]i): Redefine using :GPR.
* config/mips/mips.md (mfhilo_[sd]i): Redefine using :GPR. Add mode attribute. From-SVN: r86420
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@ -1,3 +1,8 @@
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2004-08-23 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips.md (mfhilo_[sd]i): Redefine using :GPR. Add mode
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attribute.
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2004-08-23 Richard Sandiford <rsandifo@redhat.com>
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2004-08-23 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips.md (length): Don't use mips_fetch_insns for indexed
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* config/mips/mips.md (length): Don't use mips_fetch_insns for indexed
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@ -4087,23 +4087,15 @@ beq\t%2,%.,1b\;\
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;; We cope with this by making the mflo and mfhi patterns use both HI and LO.
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;; We cope with this by making the mflo and mfhi patterns use both HI and LO.
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;; Operand 1 is the register we want, operand 2 is the other one.
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;; Operand 1 is the register we want, operand 2 is the other one.
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(define_insn "mfhilo_di"
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(define_insn "mfhilo_<mode>"
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[(set (match_operand:DI 0 "register_operand" "=d,d")
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[(set (match_operand:GPR 0 "register_operand" "=d,d")
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(unspec:DI [(match_operand:DI 1 "register_operand" "h,l")
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(unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
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(match_operand:DI 2 "register_operand" "l,h")]
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(match_operand:GPR 2 "register_operand" "l,h")]
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UNSPEC_MFHILO))]
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UNSPEC_MFHILO))]
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"TARGET_64BIT"
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"mf%1\t%0"
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[(set_attr "type" "mfhilo")])
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(define_insn "mfhilo_si"
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[(set (match_operand:SI 0 "register_operand" "=d,d")
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(unspec:SI [(match_operand:SI 1 "register_operand" "h,l")
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(match_operand:SI 2 "register_operand" "l,h")]
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UNSPEC_MFHILO))]
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""
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""
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"mf%1\t%0"
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"mf%1\t%0"
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[(set_attr "type" "mfhilo")])
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[(set_attr "type" "mfhilo")
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(set_attr "mode" "<MODE>")])
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;; Patterns for loading or storing part of a paired floating point
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;; Patterns for loading or storing part of a paired floating point
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;; register. We need them because odd-numbered floating-point registers
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;; register. We need them because odd-numbered floating-point registers
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