OpenE2K
/
gcc
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

[ARM][3/3] Recognise bitwise operations leading to SImode rev16 

* config/arm/arm.md (arm_rev16si2): New pattern.
	(arm_rev16si2_alt): Likewise.
	* config/arm/arm.c (arm_new_rtx_costs): Handle rev16 case.

	* gcc.target/arm/rev16.c: New test.

From-SVN: r209705
This commit is contained in:
Kyrylo Tkachov 2014-04-23 15:29:06 +00:00 committed by Kyrylo Tkachov
parent f7d5cf8df3
commit ea1e916837
5 changed files with 93 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
gcc/ChangeLog
View File

@ -1,3 +1,9 @@
2014-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.md (arm_rev16si2): New pattern.
(arm_rev16si2_alt): Likewise.
* config/arm/arm.c (arm_new_rtx_costs): Handle rev16 case.
2014-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.md (rev16<mode>2): New pattern.

11
gcc/config/arm/arm.c
View File

@ -9899,8 +9899,17 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
/* Vector mode? */
*cost = LIBCALL_COST (2);
return false;
case IOR:
if (mode == SImode && arm_arch6 && aarch_rev16_p (x))
{
*cost = COSTS_N_INSNS (1);
if (speed_p)
*cost += extra_cost->alu.rev;
case AND: case XOR: case IOR:
return true;
}
/* Fall through. */
case AND: case XOR:
if (mode == SImode)
{
enum rtx_code subcode = GET_CODE (XEXP (x, 0));

38
gcc/config/arm/arm.md
View File

@ -12690,6 +12690,44 @@
(set_attr "type" "rev")]
)
;; There are no canonicalisation rules for the position of the lshiftrt, ashift
;; operations within an IOR/AND RTX, therefore we have two patterns matching
;; each valid permutation.
(define_insn "arm_rev16si2"
[(set (match_operand:SI 0 "register_operand" "=l,l,r")
(ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "l,l,r")
(const_int 8))
(match_operand:SI 3 "const_int_operand" "n,n,n"))
(and:SI (lshiftrt:SI (match_dup 1)
(const_int 8))
(match_operand:SI 2 "const_int_operand" "n,n,n"))))]
"arm_arch6
&& aarch_rev16_shleft_mask_imm_p (operands[3], SImode)
&& aarch_rev16_shright_mask_imm_p (operands[2], SImode)"
"rev16\\t%0, %1"
[(set_attr "arch" "t1,t2,32")
(set_attr "length" "2,2,4")
(set_attr "type" "rev")]
)
(define_insn "arm_rev16si2_alt"
[(set (match_operand:SI 0 "register_operand" "=l,l,r")
(ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "l,l,r")
(const_int 8))
(match_operand:SI 2 "const_int_operand" "n,n,n"))
(and:SI (ashift:SI (match_dup 1)
(const_int 8))
(match_operand:SI 3 "const_int_operand" "n,n,n"))))]
"arm_arch6
&& aarch_rev16_shleft_mask_imm_p (operands[3], SImode)
&& aarch_rev16_shright_mask_imm_p (operands[2], SImode)"
"rev16\\t%0, %1"
[(set_attr "arch" "t1,t2,32")
(set_attr "length" "2,2,4")
(set_attr "type" "rev")]
)
(define_expand "bswaphi2"
[(set (match_operand:HI 0 "s_register_operand" "=r")
(bswap:HI (match_operand:HI 1 "s_register_operand" "r")))]

4
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,7 @@
2014-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gcc.target/arm/rev16.c: New test.
2014-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gcc.target/aarch64/rev16_1.c: New test.

35
gcc/testsuite/gcc.target/arm/rev16.c Normal file
View File

@ -0,0 +1,35 @@
/* { dg-options "-O2" } */
/* { dg-do run } */
extern void abort (void);
typedef unsigned int __u32;
__u32
__rev16_32_alt (__u32 x)
{
return (((__u32)(x) & (__u32)0xff00ff00UL) >> 8)
| (((__u32)(x) & (__u32)0x00ff00ffUL) << 8);
}
__u32
__rev16_32 (__u32 x)
{
return (((__u32)(x) & (__u32)0x00ff00ffUL) << 8)
| (((__u32)(x) & (__u32)0xff00ff00UL) >> 8);
}
int
main (void)
{
volatile __u32 in32 = 0x12345678;
volatile __u32 expected32 = 0x34127856;
if (__rev16_32 (in32) != expected32)
abort ();
if (__rev16_32_alt (in32) != expected32)
abort ();
return 0;
}