[ARM] Implement support for ACLE Coprocessor MCR and MRC intrinsics
gcc/ChangeLog: 2017-01-06 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/arm/arm.md (<mcr>): New. (<mrc>): New. * config/arm/arm.c (arm_coproc_builtin_available): Add support for mcr, mrc, mcr2 and mrc2. * config/arm/arm-builtins.c (MCR_QUALIFIERS): Define to... (arm_mcr_qualifiers): ... this. New. (MRC_QUALIFIERS): Define to ... (arm_mrc_qualifiers): ... this. New. (MCR_QUALIFIERS): Define to ... (arm_mcr_qualifiers): ... this. New. * config/arm/arm_acle.h (__arm_mcr, __arm_mrc, __arm_mcr2, __arm_mrc2): New. * config/arm/arm_acle_builtins.def (mcr, mcr2, mrc, mrc2): New. * config/arm/iterators.md (MCRI, mcr, MCR, MRCI, mrc, MRC): New. * config/arm/unspecs.md (VUNSPEC_MCR, VUNSPEC_MCR2, VUNSPEC_MRC, VUNSPEC_MRC2): New. gcc/testsuite/ChangeLog: 2017-01-06 Andre Vieira <andre.simoesdiasvieira@arm.com> * gcc.target/arm/acle/mcr.c: New. * gcc.target/arm/acle/mrc.c: New. * gcc.target/arm/acle/mcr2.c: New. * gcc.target/arm/acle/mrc2.c: New. From-SVN: r244174
This commit is contained in:
Andre Vieira
Andre Vieira
parent
3811581f8b
commit
ecc9a25b97
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@ -1,3 +1,22 @@
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2017-01-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/arm/arm.md (<mcr>): New.
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(<mrc>): New.
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* config/arm/arm.c (arm_coproc_builtin_available): Add
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support for mcr, mrc, mcr2 and mrc2.
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* config/arm/arm-builtins.c (MCR_QUALIFIERS): Define to...
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(arm_mcr_qualifiers): ... this. New.
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(MRC_QUALIFIERS): Define to ...
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(arm_mrc_qualifiers): ... this. New.
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(MCR_QUALIFIERS): Define to ...
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(arm_mcr_qualifiers): ... this. New.
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* config/arm/arm_acle.h (__arm_mcr, __arm_mrc, __arm_mcr2,
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__arm_mrc2): New.
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* config/arm/arm_acle_builtins.def (mcr, mcr2, mrc, mrc2): New.
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* config/arm/iterators.md (MCRI, mcr, MCR, MRCI, mrc, MRC): New.
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* config/arm/unspecs.md (VUNSPEC_MCR, VUNSPEC_MCR2, VUNSPEC_MRC,
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VUNSPEC_MRC2): New.
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2017-01-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/arm/arm.md (*ldc): New.
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@ -197,6 +197,26 @@ arm_stc_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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#define STC_QUALIFIERS \
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(arm_stc_qualifiers)
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/* void (unsigned immediate, unsigned immediate, T, unsigned immediate,
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unsigned immediate, unsigned immediate). */
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static enum arm_type_qualifiers
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arm_mcr_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_void, qualifier_unsigned_immediate,
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qualifier_unsigned_immediate, qualifier_none,
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qualifier_unsigned_immediate, qualifier_unsigned_immediate,
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qualifier_unsigned_immediate };
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#define MCR_QUALIFIERS \
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(arm_mcr_qualifiers)
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/* T (unsigned immediate, unsigned immediate, unsigned immediate,
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unsigned immediate, unsigned immediate). */
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static enum arm_type_qualifiers
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arm_mrc_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_none, qualifier_unsigned_immediate,
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qualifier_unsigned_immediate, qualifier_unsigned_immediate,
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qualifier_unsigned_immediate, qualifier_unsigned_immediate };
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#define MRC_QUALIFIERS \
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(arm_mrc_qualifiers)
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/* The first argument (return type) of a store should be void type,
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which we represent with qualifier_void. Their first operand will be
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a DImode pointer to the location to store to, so we must use
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@ -30908,6 +30908,8 @@ arm_coproc_builtin_available (enum unspecv builtin)
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case VUNSPEC_LDCL:
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case VUNSPEC_STC:
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case VUNSPEC_STCL:
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case VUNSPEC_MCR:
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case VUNSPEC_MRC:
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if (arm_arch4)
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return true;
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break;
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@ -30916,6 +30918,8 @@ arm_coproc_builtin_available (enum unspecv builtin)
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case VUNSPEC_LDC2L:
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case VUNSPEC_STC2:
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case VUNSPEC_STC2L:
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case VUNSPEC_MCR2:
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case VUNSPEC_MRC2:
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/* Only present in ARMv5*, ARMv6 (but not ARMv6-M), ARMv7* and
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ARMv8-{A,M}. */
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if (arm_arch5)
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@ -11977,6 +11977,45 @@
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(mem:SI (match_operand:SI 2 "s_register_operand"))] STCI)]
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"arm_coproc_builtin_available (VUNSPEC_<STC>)")
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(define_insn "<mcr>"
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[(unspec_volatile [(match_operand:SI 0 "immediate_operand" "n")
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(match_operand:SI 1 "immediate_operand" "n")
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(match_operand:SI 2 "s_register_operand" "r")
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(match_operand:SI 3 "immediate_operand" "n")
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(match_operand:SI 4 "immediate_operand" "n")
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(match_operand:SI 5 "immediate_operand" "n")] MCRI)
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(use (match_dup 2))]
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"arm_coproc_builtin_available (VUNSPEC_<MCR>)"
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{
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arm_const_bounds (operands[0], 0, 16);
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arm_const_bounds (operands[1], 0, 8);
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arm_const_bounds (operands[3], 0, (1 << 5));
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arm_const_bounds (operands[4], 0, (1 << 5));
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arm_const_bounds (operands[5], 0, 8);
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return "<mcr>\\tp%c0, %1, %2, CR%c3, CR%c4, %5";
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}
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[(set_attr "length" "4")
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(set_attr "type" "coproc")])
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(define_insn "<mrc>"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(unspec_volatile [(match_operand:SI 1 "immediate_operand" "n")
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(match_operand:SI 2 "immediate_operand" "n")
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(match_operand:SI 3 "immediate_operand" "n")
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(match_operand:SI 4 "immediate_operand" "n")
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(match_operand:SI 5 "immediate_operand" "n")] MRCI))]
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"arm_coproc_builtin_available (VUNSPEC_<MRC>)"
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{
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arm_const_bounds (operands[1], 0, 16);
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arm_const_bounds (operands[2], 0, 8);
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arm_const_bounds (operands[3], 0, (1 << 5));
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arm_const_bounds (operands[4], 0, (1 << 5));
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arm_const_bounds (operands[5], 0, 8);
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return "<mrc>\\tp%c1, %2, %0, CR%c3, CR%c4, %5";
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}
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[(set_attr "length" "4")
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(set_attr "type" "coproc")])
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;; Vector bits common to IWMMXT and Neon
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(include "vec-common.md")
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;; Load the Intel Wireless Multimedia Extension patterns
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@ -68,6 +68,22 @@ __arm_stcl (const unsigned int __coproc, const unsigned int __CRd,
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{
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return __builtin_arm_stcl (__coproc, __CRd, __p);
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}
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__extension__ static __inline void __attribute__ ((__always_inline__))
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__arm_mcr (const unsigned int __coproc, const unsigned int __opc1,
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uint32_t __value, const unsigned int __CRn, const unsigned int __CRm,
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const unsigned int __opc2)
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{
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return __builtin_arm_mcr (__coproc, __opc1, __value, __CRn, __CRm, __opc2);
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}
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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__arm_mrc (const unsigned int __coproc, const unsigned int __opc1,
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const unsigned int __CRn, const unsigned int __CRm,
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const unsigned int __opc2)
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{
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return __builtin_arm_mrc (__coproc, __opc1, __CRn, __CRm, __opc2);
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}
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#if __ARM_ARCH >= 5
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__extension__ static __inline void __attribute__ ((__always_inline__))
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__arm_cdp2 (const unsigned int __coproc, const unsigned int __opc1,
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@ -104,6 +120,22 @@ __arm_stc2l (const unsigned int __coproc, const unsigned int __CRd,
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{
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return __builtin_arm_stc2l (__coproc, __CRd, __p);
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}
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__extension__ static __inline void __attribute__ ((__always_inline__))
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__arm_mcr2 (const unsigned int __coproc, const unsigned int __opc1,
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uint32_t __value, const unsigned int __CRn,
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const unsigned int __CRm, const unsigned int __opc2)
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{
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return __builtin_arm_mcr2 (__coproc, __opc1, __value, __CRn, __CRm, __opc2);
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}
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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__arm_mrc2 (const unsigned int __coproc, const unsigned int __opc1,
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const unsigned int __CRn, const unsigned int __CRm,
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const unsigned int __opc2)
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{
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return __builtin_arm_mrc2 (__coproc, __opc1, __CRn, __CRm, __opc2);
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}
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#endif /* __ARM_ARCH >= 5. */
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#endif /* (!__thumb__ || __thumb2__) && __ARM_ARCH >= 4. */
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@ -34,3 +34,7 @@ VAR1 (STC, stc, void)
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VAR1 (STC, stc2, void)
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VAR1 (STC, stcl, void)
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VAR1 (STC, stc2l, void)
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VAR1 (MCR, mcr, void)
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VAR1 (MCR, mcr2, void)
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VAR1 (MRC, mrc, si)
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VAR1 (MRC, mrc2, si)
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@ -964,3 +964,15 @@
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(VUNSPEC_STCL "stcl") (VUNSPEC_STC2L "stc2l")])
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(define_int_attr STC [(VUNSPEC_STC "STC") (VUNSPEC_STC2 "STC2")
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(VUNSPEC_STCL "STCL") (VUNSPEC_STC2L "STC2L")])
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;; An iterator for the MCR coprocessor instructions
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(define_int_iterator MCRI [VUNSPEC_MCR VUNSPEC_MCR2])
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(define_int_attr mcr [(VUNSPEC_MCR "mcr") (VUNSPEC_MCR2 "mcr2")])
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(define_int_attr MCR [(VUNSPEC_MCR "MCR") (VUNSPEC_MCR2 "MCR2")])
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;; An iterator for the MRC coprocessor instructions
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(define_int_iterator MRCI [VUNSPEC_MRC VUNSPEC_MRC2])
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(define_int_attr mrc [(VUNSPEC_MRC "mrc") (VUNSPEC_MRC2 "mrc2")])
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(define_int_attr MRC [(VUNSPEC_MRC "MRC") (VUNSPEC_MRC2 "MRC2")])
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@ -160,6 +160,10 @@
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VUNSPEC_STC2 ; Represent the coprocessor stc2 instruction.
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VUNSPEC_STCL ; Represent the coprocessor stcl instruction.
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VUNSPEC_STC2L ; Represent the coprocessor stc2l instruction.
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VUNSPEC_MCR ; Represent the coprocessor mcr instruction.
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VUNSPEC_MCR2 ; Represent the coprocessor mcr2 instruction.
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VUNSPEC_MRC ; Represent the coprocessor mrc instruction.
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VUNSPEC_MRC2 ; Represent the coprocessor mrc2 instruction.
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])
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;; Enumerators for NEON unspecs.
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@ -1,3 +1,10 @@
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2017-01-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* gcc.target/arm/acle/mcr.c: New.
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* gcc.target/arm/acle/mrc.c: New.
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* gcc.target/arm/acle/mcr2.c: New.
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* gcc.target/arm/acle/mrc2.c: New.
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2017-01-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* gcc.target/arm/acle/ldc: New.
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@ -0,0 +1,16 @@
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/* Test the mcr ACLE intrinsic. */
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/* { dg-do assemble } */
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/* { dg-options "-save-temps" } */
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/* { dg-require-effective-target arm_coproc1_ok } */
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#include "arm_acle.h"
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void test_mcr (uint32_t a)
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{
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a += 77;
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__arm_mcr (10, 5, a, 3, 4, 7);
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}
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/* { dg-final { scan-assembler "add\[^\n\]*#77\n" } } */
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/* { dg-final { scan-assembler "mcr\tp10, #5, r\[r0-9\]*, CR3, CR4, #7\n" } } */
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@ -0,0 +1,16 @@
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/* Test the mcr2 ACLE intrinsic. */
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/* { dg-do assemble } */
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/* { dg-options "-save-temps" } */
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/* { dg-require-effective-target arm_coproc2_ok } */
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#include "arm_acle.h"
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void test_mcr2 (uint32_t a)
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{
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a += 77;
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__arm_mcr2 (10, 5, a, 3, 4, 7);
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}
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/* { dg-final { scan-assembler "add\[^\n\]*#77\n" } } */
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/* { dg-final { scan-assembler "mcr2\tp10, #5, r\[r0-9\]*, CR3, CR4, #7\n" } } */
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@ -0,0 +1,14 @@
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/* Test the mrc ACLE intrinsic. */
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/* { dg-do assemble } */
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/* { dg-options "-save-temps" } */
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/* { dg-require-effective-target arm_coproc1_ok } */
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#include "arm_acle.h"
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uint32_t test_mrc (void)
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{
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return __arm_mrc (10, 0, 0, 15, 3);
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}
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/* { dg-final { scan-assembler "mrc\tp10, #0, r\[r0-9\]*, CR0, CR15, #3\n" } } */
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/* Test the mrc2 ACLE intrinsic. */
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/* { dg-do assemble } */
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/* { dg-options "-save-temps" } */
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/* { dg-require-effective-target arm_coproc2_ok } */
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#include "arm_acle.h"
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uint32_t test_mrc2 (void)
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{
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return __arm_mrc2 (10, 0, 0, 15, 3);
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}
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/* { dg-final { scan-assembler "mrc2\tp10, #0, r\[r0-9\]*, CR0, CR15, #3\n" } } */
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