constraints.md: New file.
* config/m32r/constraints.md: New file. * config/m32r/m32r.c: Include tm-constrs.h. (small_data_operand): Use satisfies_constraint_* instead of macro. (addr24_operand, gen_compare): Likewise. * config/m32r/m32r.h (REG_CLASS_FROM_LETTER): Remove. (INT8_P, UPPER16_P, UINT32_P, UINT5_P, INVERTED_SIGNED_8BIT, CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Likewise. * config/m32r/m32r.md: Include constraints.md. (movsi_insn): Use satisfies_constraint_* instead of macro. (andsi3, iorsi3, xorsi3, seq_insn+1, sne): Likewise. * config/m32r/predicates.md (conditional_move_operand): Likewise. (two_insn_const_operand, int8_operand, uint16_operand, reg_or_int16_operand, reg_or_uint16_operand, reg_or_cmp_int16_operand, cmp_int16_operand, seth_add3_operand): Likewise. From-SVN: r126265
This commit is contained in:
parent
db430f6a2a
commit
fbaeb717be
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@ -1,3 +1,22 @@
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2007-07-01 Kaz Kojima <kkojima@gcc.gnu.org>
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* config/m32r/constraints.md: New file.
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* config/m32r/m32r.c: Include tm-constrs.h.
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(small_data_operand): Use satisfies_constraint_* instead of macro.
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(addr24_operand, gen_compare): Likewise.
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* config/m32r/m32r.h (REG_CLASS_FROM_LETTER): Remove.
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(INT8_P, UPPER16_P, UINT32_P, UINT5_P, INVERTED_SIGNED_8BIT,
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CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P,
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EXTRA_CONSTRAINT): Likewise.
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* config/m32r/m32r.md: Include constraints.md.
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(*movsi_insn): Use satisfies_constraint_* instead of macro.
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(andsi3, iorsi3, xorsi3, seq_insn+1, sne): Likewise.
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* config/m32r/predicates.md (conditional_move_operand): Likewise.
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(two_insn_const_operand, int8_operand, uint16_operand,
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reg_or_int16_operand, reg_or_uint16_operand,
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reg_or_cmp_int16_operand, cmp_int16_operand,
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seth_add3_operand): Likewise.
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2007-07-03 Eric Christopher <echristo@gmail.com>
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2007-07-03 Eric Christopher <echristo@gmail.com>
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* libgcc2.h: Conditionally declare __bswapsi2 and
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* libgcc2.h: Conditionally declare __bswapsi2 and
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@ -0,0 +1,131 @@
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;; Constraint definitions for Renesas M32R cpu for GNU C compiler
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;; Copyright (C) 2007 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 2, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING. If not, write to
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;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
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;; Boston, MA 02110-1301, USA.
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;; The letters I, J, K, L, M, N, O, P in a register constraint string
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;; can be used to stand for particular ranges of immediate operands.
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;; The letters Q, R, S, T, U are used to segregate specific types of
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;; operands, usually memory references, for the target machine.
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;;
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;; I is used for 8-bit signed immediates.
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;; J is used for 16-bit signed immediates.
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;; K is used for 16-bit unsigned immediates.
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;; L is used for 16-bit immediates left shifted by 16 (sign ???).
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;; M is used for 24-bit unsigned immediates.
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;; N is used for 8-bit signed immediates for compares
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;; (values in the range -127 to +128).
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;; O is used for 5-bit unsigned immediates (shift count).
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;; P is used for 16-bit signed immediates for compares
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;; (values in the range -32767 to +32768).
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;;
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;; Q is for symbolic addresses loadable with ld24.
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;; R is for symbolic addresses when ld24 can't be used.
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;; S is for stores with pre {inc,dec}rement
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;; T is for indirect of a pointer.
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;; U is for loads with post increment.
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;;
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;; Register constraints
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(define_register_constraint "a" "ACCUM_REGS"
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"@internal")
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(define_register_constraint "c" "CARRY_REG"
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"@internal")
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;; Integer constraints
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(define_constraint "I"
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"8-bit signed immediate."
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(and (match_code "const_int")
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(match_test "ival >= -0x80 && ival <= 0x7f")))
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(define_constraint "J"
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"16-bit signed immediate."
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(and (match_code "const_int")
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(match_test "ival >= -0x8000 && ival <= 0x7fff")))
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(define_constraint "K"
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"16-bit unsigned immediate."
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(and (match_code "const_int")
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(match_test "(unsigned HOST_WIDE_INT) ival <= 0x0000ffff")))
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(define_constraint "L"
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"16-bit signed immediate left shifted by 16."
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(and (match_code "const_int")
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(match_test "(ival & 0xffff) == 0")
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(match_test "(ival >> 16) >= -0x8000 && (ival >> 16) <= 0x7fff")))
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(define_constraint "M"
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"24-bit unsigned immediate."
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(and (match_code "const_int")
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(match_test "(unsigned HOST_WIDE_INT) ival <= 0x00ffffff")))
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(define_constraint "N"
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"8-bit signed immediate for compare."
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(and (match_code "const_int")
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(match_test "ival >= -127 && ival <= 128")))
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(define_constraint "O"
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"5-bit unsigned immediate."
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(and (match_code "const_int")
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(match_test "ival >= 0 && ival < 32")))
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(define_constraint "P"
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"16-bit signed immediate for compare."
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(and (match_code "const_int")
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(match_test "ival >= -0x7fff && ival <= 0x8000")))
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;; Floating-point constraints
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(define_constraint "G"
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"Double constant loadable with 2 ldi insns."
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(and (match_code "const_double")
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(match_test "easy_di_const (op)")))
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(define_constraint "H"
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"Double constant loadable with movdf."
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(and (match_code "const_double")
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(match_test "easy_df_const (op)")))
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;; Extra constraints
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(define_constraint "Q"
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"A symbolic addresse loadable when ld24."
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(ior (and (match_test "TARGET_ADDR24")
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(match_test "GET_CODE (op) == LABEL_REF"))
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(match_test "addr24_operand (op, VOIDmode)")))
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(define_constraint "R"
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"A symbolic addresse loadable with ld24 can't be used."
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(ior (and (match_test "TARGET_ADDR32")
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(match_test "GET_CODE (op) == LABEL_REF"))
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(match_test "addr32_operand (op, VOIDmode)")))
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(define_constraint "S"
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"A store with pre {inc,dec}rement."
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(and (match_code "mem")
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(match_test "STORE_PREINC_PREDEC_P (GET_MODE (op), XEXP (op, 0))")))
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(define_constraint "T"
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"An indirect of a pointer."
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(and (match_code "mem")
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(match_test "memreg_operand (op, GET_MODE (op))")))
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(define_constraint "U"
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"A load with post increment."
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(and (match_code "mem")
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(match_test "LOAD_POSTINC_P (GET_MODE (op), XEXP (op, 0))")))
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@ -42,6 +42,7 @@
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#include "tm_p.h"
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#include "tm_p.h"
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#include "target.h"
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#include "target.h"
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#include "target-def.h"
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#include "target-def.h"
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#include "tm-constrs.h"
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/* Save the operands last given to a compare for use when we
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/* Save the operands last given to a compare for use when we
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generate a scc or bcc insn. */
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generate a scc or bcc insn. */
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@ -508,8 +509,7 @@ small_data_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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if (GET_CODE (op) == CONST
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if (GET_CODE (op) == CONST
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&& GET_CODE (XEXP (op, 0)) == PLUS
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&& GET_CODE (XEXP (op, 0)) == PLUS
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&& GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
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&& GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
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&& GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
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&& satisfies_constraint_J (XEXP (XEXP (op, 0), 1)))
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&& INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
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return SYMBOL_REF_SMALL_P (XEXP (XEXP (op, 0), 0));
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return SYMBOL_REF_SMALL_P (XEXP (XEXP (op, 0), 0));
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return 0;
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return 0;
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@ -533,8 +533,7 @@ addr24_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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else if (GET_CODE (op) == CONST
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else if (GET_CODE (op) == CONST
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&& GET_CODE (XEXP (op, 0)) == PLUS
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&& GET_CODE (XEXP (op, 0)) == PLUS
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&& GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
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&& GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
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&& GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
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&& satisfies_constraint_M (XEXP (XEXP (op, 0), 1)))
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&& UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1))))
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sym = XEXP (XEXP (op, 0), 0);
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sym = XEXP (XEXP (op, 0), 0);
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else
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else
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return 0;
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return 0;
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@ -691,8 +690,7 @@ gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare)
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switch (compare_code)
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switch (compare_code)
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{
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{
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case EQ:
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case EQ:
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if (GET_CODE (y) == CONST_INT
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if (satisfies_constraint_P (y) /* Reg equal to small const. */
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&& CMP_INT16_P (INTVAL (y)) /* Reg equal to small const. */
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&& y != const0_rtx)
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&& y != const0_rtx)
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{
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{
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rtx tmp = gen_reg_rtx (SImode);
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rtx tmp = gen_reg_rtx (SImode);
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@ -718,7 +716,7 @@ gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare)
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case LT:
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case LT:
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if (register_operand (y, SImode)
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if (register_operand (y, SImode)
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|| (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
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|| satisfies_constraint_P (y))
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{
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{
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rtx tmp = gen_reg_rtx (SImode); /* Reg compared to reg. */
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rtx tmp = gen_reg_rtx (SImode); /* Reg compared to reg. */
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@ -758,7 +756,7 @@ gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare)
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case LTU:
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case LTU:
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if (register_operand (y, SImode)
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if (register_operand (y, SImode)
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|| (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
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|| satisfies_constraint_P (y))
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{
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{
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rtx tmp = gen_reg_rtx (SImode); /* Reg (unsigned) compared to reg. */
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rtx tmp = gen_reg_rtx (SImode); /* Reg (unsigned) compared to reg. */
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@ -814,8 +812,7 @@ gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare)
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/* Reg/smallconst equal comparison. */
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/* Reg/smallconst equal comparison. */
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if (compare_code == EQ
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if (compare_code == EQ
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&& GET_CODE (y) == CONST_INT
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&& satisfies_constraint_P (y))
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&& CMP_INT16_P (INTVAL (y)))
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{
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{
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rtx tmp = gen_reg_rtx (SImode);
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rtx tmp = gen_reg_rtx (SImode);
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@ -1,6 +1,6 @@
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/* Definitions of target machine for GNU compiler, Renesas M32R cpu.
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/* Definitions of target machine for GNU compiler, Renesas M32R cpu.
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Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
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Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
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2005, 2006 Free Software Foundation, Inc.
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2005, 2006, 2007 Free Software Foundation, Inc.
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This file is part of GCC.
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This file is part of GCC.
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@ -671,11 +671,6 @@ extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
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#define INDEX_REG_CLASS GENERAL_REGS
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#define INDEX_REG_CLASS GENERAL_REGS
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#define BASE_REG_CLASS GENERAL_REGS
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#define BASE_REG_CLASS GENERAL_REGS
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#define REG_CLASS_FROM_LETTER(C) \
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( (C) == 'c' ? CARRY_REG \
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: (C) == 'a' ? ACCUM_REGS \
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: NO_REGS)
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/* These assume that REGNO is a hard or pseudo reg number.
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/* These assume that REGNO is a hard or pseudo reg number.
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They give nonzero only if REGNO is a hard reg of the suitable class
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They give nonzero only if REGNO is a hard reg of the suitable class
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or a pseudo reg currently allocated to a suitable hard reg.
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or a pseudo reg currently allocated to a suitable hard reg.
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@ -699,85 +694,16 @@ extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
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#define CLASS_MAX_NREGS(CLASS, MODE) \
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#define CLASS_MAX_NREGS(CLASS, MODE) \
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((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
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((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
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/* The letters I, J, K, L, M, N, O, P in a register constraint string
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can be used to stand for particular ranges of immediate operands.
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This macro defines what the ranges are.
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C is the letter, and VALUE is a constant value.
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Return 1 if VALUE is in the range specified by C. */
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/* 'I' is used for 8-bit signed immediates.
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'J' is used for 16-bit signed immediates.
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'K' is used for 16-bit unsigned immediates.
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'L' is used for 16-bit immediates left shifted by 16 (sign ???).
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'M' is used for 24-bit unsigned immediates.
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'N' is used for any 32-bit non-symbolic value.
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'O' is used for 5-bit unsigned immediates (shift count).
|
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'P' is used for 16-bit signed immediates for compares
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(values in the range -32767 to +32768). */
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/* Return true if a value is inside a range. */
|
/* Return true if a value is inside a range. */
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#define IN_RANGE_P(VALUE, LOW, HIGH) \
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#define IN_RANGE_P(VALUE, LOW, HIGH) \
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(((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \
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(((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \
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<= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW))))
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<= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW))))
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/* Local to this file. */
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/* Some range macros. */
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#define INT8_P(X) ((X) >= - 0x80 && (X) <= 0x7f)
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#define INT16_P(X) ((X) >= - 0x8000 && (X) <= 0x7fff)
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#define INT16_P(X) ((X) >= - 0x8000 && (X) <= 0x7fff)
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#define CMP_INT16_P(X) ((X) >= - 0x7fff && (X) <= 0x8000)
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#define CMP_INT16_P(X) ((X) >= - 0x7fff && (X) <= 0x8000)
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#define UPPER16_P(X) (((X) & 0xffff) == 0 \
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&& ((X) >> 16) >= - 0x8000 \
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&& ((X) >> 16) <= 0x7fff)
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#define UINT16_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff)
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#define UINT16_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff)
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#define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff)
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#define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff)
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#define UINT32_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0xffffffff)
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#define UINT5_P(X) ((X) >= 0 && (X) < 32)
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#define INVERTED_SIGNED_8BIT(VAL) ((VAL) >= -127 && (VAL) <= 128)
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#define CONST_OK_FOR_LETTER_P(VALUE, C) \
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( (C) == 'I' ? INT8_P (VALUE) \
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: (C) == 'J' ? INT16_P (VALUE) \
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|
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: (C) == 'K' ? UINT16_P (VALUE) \
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: (C) == 'L' ? UPPER16_P (VALUE) \
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|
||||||
: (C) == 'M' ? UINT24_P (VALUE) \
|
|
||||||
: (C) == 'N' ? INVERTED_SIGNED_8BIT (VALUE) \
|
|
||||||
: (C) == 'O' ? UINT5_P (VALUE) \
|
|
||||||
: (C) == 'P' ? CMP_INT16_P (VALUE) \
|
|
||||||
: 0)
|
|
||||||
|
|
||||||
/* Similar, but for floating constants, and defining letters G and H.
|
|
||||||
Here VALUE is the CONST_DOUBLE rtx itself.
|
|
||||||
For the m32r, handle a few constants inline.
|
|
||||||
??? We needn't treat DI and DF modes differently, but for now we do. */
|
|
||||||
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
|
|
||||||
( (C) == 'G' ? easy_di_const (VALUE) \
|
|
||||||
: (C) == 'H' ? easy_df_const (VALUE) \
|
|
||||||
: 0)
|
|
||||||
|
|
||||||
/* A C expression that defines the optional machine-dependent constraint
|
|
||||||
letters that can be used to segregate specific types of operands,
|
|
||||||
usually memory references, for the target machine. It should return 1 if
|
|
||||||
VALUE corresponds to the operand type represented by the constraint letter
|
|
||||||
C. If C is not defined as an extra constraint, the value returned should
|
|
||||||
be 0 regardless of VALUE. */
|
|
||||||
/* Q is for symbolic addresses loadable with ld24.
|
|
||||||
R is for symbolic addresses when ld24 can't be used.
|
|
||||||
S is for stores with pre {inc,dec}rement
|
|
||||||
T is for indirect of a pointer.
|
|
||||||
U is for loads with post increment. */
|
|
||||||
|
|
||||||
#define EXTRA_CONSTRAINT(VALUE, C) \
|
|
||||||
( (C) == 'Q' ? ((TARGET_ADDR24 && GET_CODE (VALUE) == LABEL_REF) \
|
|
||||||
|| addr24_operand (VALUE, VOIDmode)) \
|
|
||||||
: (C) == 'R' ? ((TARGET_ADDR32 && GET_CODE (VALUE) == LABEL_REF) \
|
|
||||||
|| addr32_operand (VALUE, VOIDmode)) \
|
|
||||||
: (C) == 'S' ? (GET_CODE (VALUE) == MEM \
|
|
||||||
&& STORE_PREINC_PREDEC_P (GET_MODE (VALUE), \
|
|
||||||
XEXP (VALUE, 0))) \
|
|
||||||
: (C) == 'T' ? (GET_CODE (VALUE) == MEM \
|
|
||||||
&& memreg_operand (VALUE, GET_MODE (VALUE))) \
|
|
||||||
: (C) == 'U' ? (GET_CODE (VALUE) == MEM \
|
|
||||||
&& LOAD_POSTINC_P (GET_MODE (VALUE), \
|
|
||||||
XEXP (VALUE, 0))) \
|
|
||||||
: 0)
|
|
||||||
|
|
||||||
/* Stack layout and stack pointer usage. */
|
/* Stack layout and stack pointer usage. */
|
||||||
|
|
||||||
|
|
|
@ -200,6 +200,7 @@
|
||||||
|
|
||||||
|
|
||||||
(include "predicates.md")
|
(include "predicates.md")
|
||||||
|
(include "constraints.md")
|
||||||
|
|
||||||
;; Expand prologue as RTL
|
;; Expand prologue as RTL
|
||||||
(define_expand "prologue"
|
(define_expand "prologue"
|
||||||
|
@ -388,14 +389,13 @@
|
||||||
return \"ld %0,%1\";
|
return \"ld %0,%1\";
|
||||||
|
|
||||||
case CONST_INT:
|
case CONST_INT:
|
||||||
value = INTVAL (operands[1]);
|
if (satisfies_constraint_J (operands[1]))
|
||||||
if (INT16_P (value))
|
|
||||||
return \"ldi %0,%#%1\\t; %X1\";
|
return \"ldi %0,%#%1\\t; %X1\";
|
||||||
|
|
||||||
if (UINT24_P (value))
|
if (satisfies_constraint_M (operands[1]))
|
||||||
return \"ld24 %0,%#%1\\t; %X1\";
|
return \"ld24 %0,%#%1\\t; %X1\";
|
||||||
|
|
||||||
if (UPPER16_P (value))
|
if (satisfies_constraint_L (operands[1]))
|
||||||
return \"seth %0,%#%T1\\t; %X1\";
|
return \"seth %0,%#%T1\\t; %X1\";
|
||||||
|
|
||||||
return \"#\";
|
return \"#\";
|
||||||
|
@ -834,7 +834,7 @@
|
||||||
; (match_operand:SI 2 "int8_operand" "")))]
|
; (match_operand:SI 2 "int8_operand" "")))]
|
||||||
; "reload_completed
|
; "reload_completed
|
||||||
; && REGNO (operands[0]) != REGNO (operands[1])
|
; && REGNO (operands[0]) != REGNO (operands[1])
|
||||||
; && INT8_P (INTVAL (operands[2]))
|
; && satisfies_constraint_I (operands[2])
|
||||||
; && INTVAL (operands[2]) != 0"
|
; && INTVAL (operands[2]) != 0"
|
||||||
; [(set (match_dup 0) (match_dup 1))
|
; [(set (match_dup 0) (match_dup 1))
|
||||||
; (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
|
; (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
|
||||||
|
@ -1034,8 +1034,7 @@
|
||||||
short instructions, which might eliminate a NOP being inserted. */
|
short instructions, which might eliminate a NOP being inserted. */
|
||||||
if (optimize_size
|
if (optimize_size
|
||||||
&& m32r_not_same_reg (operands[0], operands[1])
|
&& m32r_not_same_reg (operands[0], operands[1])
|
||||||
&& GET_CODE (operands[2]) == CONST_INT
|
&& satisfies_constraint_I (operands[2]))
|
||||||
&& INT8_P (INTVAL (operands[2])))
|
|
||||||
return \"#\";
|
return \"#\";
|
||||||
|
|
||||||
else if (GET_CODE (operands[2]) == CONST_INT)
|
else if (GET_CODE (operands[2]) == CONST_INT)
|
||||||
|
@ -1066,8 +1065,7 @@
|
||||||
short instructions, which might eliminate a NOP being inserted. */
|
short instructions, which might eliminate a NOP being inserted. */
|
||||||
if (optimize_size
|
if (optimize_size
|
||||||
&& m32r_not_same_reg (operands[0], operands[1])
|
&& m32r_not_same_reg (operands[0], operands[1])
|
||||||
&& GET_CODE (operands[2]) == CONST_INT
|
&& satisfies_constraint_I (operands[2]))
|
||||||
&& INT8_P (INTVAL (operands[2])))
|
|
||||||
return \"#\";
|
return \"#\";
|
||||||
|
|
||||||
else if (GET_CODE (operands[2]) == CONST_INT)
|
else if (GET_CODE (operands[2]) == CONST_INT)
|
||||||
|
@ -1098,8 +1096,7 @@
|
||||||
short instructions, which might eliminate a NOP being inserted. */
|
short instructions, which might eliminate a NOP being inserted. */
|
||||||
if (optimize_size
|
if (optimize_size
|
||||||
&& m32r_not_same_reg (operands[0], operands[1])
|
&& m32r_not_same_reg (operands[0], operands[1])
|
||||||
&& GET_CODE (operands[2]) == CONST_INT
|
&& satisfies_constraint_I (operands[2]))
|
||||||
&& INT8_P (INTVAL (operands[2])))
|
|
||||||
return \"#\";
|
return \"#\";
|
||||||
|
|
||||||
else if (GET_CODE (operands[2]) == CONST_INT)
|
else if (GET_CODE (operands[2]) == CONST_INT)
|
||||||
|
@ -1732,8 +1729,7 @@
|
||||||
op1 = op3;
|
op1 = op3;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (GET_CODE (op2) == CONST_INT && (value = INTVAL (op2)) != 0
|
if (satisfies_constraint_P (op2) && (value = INTVAL (op2)) != 0)
|
||||||
&& CMP_INT16_P (value))
|
|
||||||
emit_insn (gen_addsi3 (op3, op1, GEN_INT (-value)));
|
emit_insn (gen_addsi3 (op3, op1, GEN_INT (-value)));
|
||||||
else
|
else
|
||||||
emit_insn (gen_xorsi3 (op3, op1, op2));
|
emit_insn (gen_xorsi3 (op3, op1, op2));
|
||||||
|
@ -1757,8 +1753,8 @@
|
||||||
if (mode != SImode)
|
if (mode != SImode)
|
||||||
FAIL;
|
FAIL;
|
||||||
|
|
||||||
if (GET_CODE (op2) != CONST_INT
|
if (GET_CODE (op2) != CONST_INT
|
||||||
|| (INTVAL (op2) != 0 && UINT16_P (INTVAL (op2))))
|
|| (INTVAL (op2) != 0 && satisfies_constraint_K (op2)))
|
||||||
{
|
{
|
||||||
rtx reg;
|
rtx reg;
|
||||||
|
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
;; Predicate definitions for Renesas M32R.
|
;; Predicate definitions for Renesas M32R.
|
||||||
;; Copyright (C) 2005 Free Software Foundation, Inc.
|
;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
|
||||||
;;
|
;;
|
||||||
;; This file is part of GCC.
|
;; This file is part of GCC.
|
||||||
;;
|
;;
|
||||||
|
@ -51,7 +51,7 @@
|
||||||
return 1;
|
return 1;
|
||||||
|
|
||||||
case CONST_INT:
|
case CONST_INT:
|
||||||
return INT8_P (INTVAL (op));
|
return satisfies_constraint_I (op);
|
||||||
|
|
||||||
default:
|
default:
|
||||||
#if 0
|
#if 0
|
||||||
|
@ -229,9 +229,9 @@
|
||||||
{
|
{
|
||||||
if (GET_CODE (op) != CONST_INT)
|
if (GET_CODE (op) != CONST_INT)
|
||||||
return 0;
|
return 0;
|
||||||
if (INT16_P (INTVAL (op))
|
if (satisfies_constraint_J (op)
|
||||||
|| UINT24_P (INTVAL (op))
|
|| satisfies_constraint_M (op)
|
||||||
|| UPPER16_P (INTVAL (op)))
|
|| satisfies_constraint_L (op))
|
||||||
return 0;
|
return 0;
|
||||||
return 1;
|
return 1;
|
||||||
})
|
})
|
||||||
|
@ -260,7 +260,7 @@
|
||||||
{
|
{
|
||||||
if (GET_CODE (op) != CONST_INT)
|
if (GET_CODE (op) != CONST_INT)
|
||||||
return 0;
|
return 0;
|
||||||
return INT8_P (INTVAL (op));
|
return satisfies_constraint_I (op);
|
||||||
})
|
})
|
||||||
|
|
||||||
;; Return true if OP is an unsigned 16-bit immediate value.
|
;; Return true if OP is an unsigned 16-bit immediate value.
|
||||||
|
@ -270,7 +270,7 @@
|
||||||
{
|
{
|
||||||
if (GET_CODE (op) != CONST_INT)
|
if (GET_CODE (op) != CONST_INT)
|
||||||
return 0;
|
return 0;
|
||||||
return UINT16_P (INTVAL (op));
|
return satisfies_constraint_K (op);
|
||||||
})
|
})
|
||||||
|
|
||||||
;; Return true if OP is a register or signed 16-bit value.
|
;; Return true if OP is a register or signed 16-bit value.
|
||||||
|
@ -282,7 +282,7 @@
|
||||||
return register_operand (op, mode);
|
return register_operand (op, mode);
|
||||||
if (GET_CODE (op) != CONST_INT)
|
if (GET_CODE (op) != CONST_INT)
|
||||||
return 0;
|
return 0;
|
||||||
return INT16_P (INTVAL (op));
|
return satisfies_constraint_J (op);
|
||||||
})
|
})
|
||||||
|
|
||||||
;; Return true if OP is a register or an unsigned 16-bit value.
|
;; Return true if OP is a register or an unsigned 16-bit value.
|
||||||
|
@ -294,7 +294,7 @@
|
||||||
return register_operand (op, mode);
|
return register_operand (op, mode);
|
||||||
if (GET_CODE (op) != CONST_INT)
|
if (GET_CODE (op) != CONST_INT)
|
||||||
return 0;
|
return 0;
|
||||||
return UINT16_P (INTVAL (op));
|
return satisfies_constraint_K (op);
|
||||||
})
|
})
|
||||||
|
|
||||||
;; Return true if OP is a register or signed 16-bit value for
|
;; Return true if OP is a register or signed 16-bit value for
|
||||||
|
@ -307,7 +307,7 @@
|
||||||
return register_operand (op, mode);
|
return register_operand (op, mode);
|
||||||
if (GET_CODE (op) != CONST_INT)
|
if (GET_CODE (op) != CONST_INT)
|
||||||
return 0;
|
return 0;
|
||||||
return CMP_INT16_P (INTVAL (op));
|
return satisfies_constraint_P (op);
|
||||||
})
|
})
|
||||||
|
|
||||||
;; Return true if OP is a register or an integer value that can be
|
;; Return true if OP is a register or an integer value that can be
|
||||||
|
@ -338,7 +338,7 @@
|
||||||
{
|
{
|
||||||
if (GET_CODE (op) != CONST_INT)
|
if (GET_CODE (op) != CONST_INT)
|
||||||
return 0;
|
return 0;
|
||||||
return CMP_INT16_P (INTVAL (op));
|
return satisfies_constraint_P (op);
|
||||||
})
|
})
|
||||||
|
|
||||||
;; Acceptable arguments to the call insn.
|
;; Acceptable arguments to the call insn.
|
||||||
|
@ -434,8 +434,7 @@
|
||||||
if (GET_CODE (op) == CONST
|
if (GET_CODE (op) == CONST
|
||||||
&& GET_CODE (XEXP (op, 0)) == PLUS
|
&& GET_CODE (XEXP (op, 0)) == PLUS
|
||||||
&& GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
|
&& GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
|
||||||
&& GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
|
&& satisfies_constraint_J (XEXP (XEXP (op, 0), 1)))
|
||||||
&& INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
|
|
||||||
return 1;
|
return 1;
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
|
Loading…
Reference in New Issue