This builds ontop of the vect_worthwhile_without_simd_p refactoring
done earlier. It was wrong in dropping the appearant double checks
for operation support since the optab check can happen with an
integer vector emulation mode and thus succeed but vector lowering
might not actually support the operation on word_mode.
The following patch adds a vect_emulated_vector_p helper and
re-instantiates the check where it was previously. It also adds
appropriate costing of the scalar stmts emitted by vector lowering
to vectorizable_operation which should be the only place such
operations are synthesized. I've also cared for the case where
the vector mode is supported but the operation is not (though
I think this will be unlikely given we're talking about plus, minus
and negate).
This fixes the observed FAIL of gcc.dg/tree-ssa/gen-vect-11b.c
with -m32 where we end up vectorizing a multiplication that ends up
being teared down to scalars again by vector lowering.
I'm not super happy about all the other places where we're now
and previously feeding scalar modes to optab checks where we
want to know whether we can vectorize sth but well.
2021-09-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/101801
PR tree-optimization/101819
* tree-vectorizer.h (vect_emulated_vector_p): Declare.
* tree-vect-loop.c (vect_emulated_vector_p): New function.
(vectorizable_reduction): Re-instantiate a check for emulated
operations.
* tree-vect-stmts.c (vectorizable_shift): Likewise.
(vectorizable_operation): Likewise. Cost emulated vector
operations according to the scalar sequence synthesized by
vector lowering.
When we build the COMPONENT_REF of a formerly volatile local off
the FRAME decl we have to make sure to mark the COMPONENT_REF
as TREE_THIS_VOLATILE. While the GIMPLE operand scanner looks
at the FIELD_DECL this is not how volatile GENERIC refs work.
2021-08-09 Richard Biener <rguenther@suse.de>
PR middle-end/101824
* tree-nested.c (get_frame_field): Mark the COMPONENT_REF as
volatile in case the variable was.
* gcc.dg/tree-ssa/pr101824.c: New testcase.
Evaluate arguments of sizeof for all types of variable size
and not just for VLAs. This fixes some issues related to
[PR29970] where statement expressions need to be evaluated
so that the size is well defined.
2021-08-10 Martin Uecker <muecker@gwdg.de>
gcc/c/
PR c/29970
* c-typeck.c (c_expr_sizeof_expr): Evaluate
size expressions for structs of variable size.
gcc/testsuite/
PR c/29970
* gcc.dg/vla-stexp-1.c: New test.
Check float_vector_all_ones_operand for vector floating-point modes to
optimize load of const floating-point all bits set vectors.
gcc/
PR target/101804
* config/i386/constraints.md (BC): Document for integer SSE
constant all bits set operand.
(BF): New constraint for const floating-point all bits set
vectors.
* config/i386/i386.c (standard_sse_constant_p): Likewise.
(standard_sse_constant_opcode): Likewise.
* config/i386/sse.md (sseconstm1): New mode attribute.
(mov<mode>_internal): Replace BC with <sseconstm1>.
gcc/testsuite/
PR target/101804
* gcc.target/i386/avx2-gather-2.c: Pass -march=skylake instead
of "-mavx2 -mtune=skylake". Scan vpcmpeqd.
gcc/ChangeLog:
* config/i386/sse.md (cond_<insn><mode>): New expander.
(VI248_AVX512VLBW): New mode iterator.
* config/i386/predicates.md
(nonimmediate_or_const_vec_dup_operand): New predicate.
gcc/testsuite/ChangeLog:
* gcc.target/i386/cond_op_shift_d-1.c: New test.
* gcc.target/i386/cond_op_shift_d-2.c: New test.
* gcc.target/i386/cond_op_shift_q-1.c: New test.
* gcc.target/i386/cond_op_shift_q-2.c: New test.
* gcc.target/i386/cond_op_shift_ud-1.c: New test.
* gcc.target/i386/cond_op_shift_ud-2.c: New test.
* gcc.target/i386/cond_op_shift_uq-1.c: New test.
* gcc.target/i386/cond_op_shift_uq-2.c: New test.
* gcc.target/i386/cond_op_shift_uw-1.c: New test.
* gcc.target/i386/cond_op_shift_uw-2.c: New test.
* gcc.target/i386/cond_op_shift_w-1.c: New test.
* gcc.target/i386/cond_op_shift_w-2.c: New test.
If the parameter is not compatible with the LHS, assume this is not really a
builtin function to avoid a trap.
gcc/
PR tree-optimization/101741
* gimple-range-fold.cc (fold_using_range::range_of_builtin_call): Check
type of parameter for toupper/tolower.
gcc/testsuite/
* gcc.dg/pr101741.c: New.
The std::regex code uses std::map and std::vector, which means that when
_GLIBCXX_DEBUG is defined it uses the debug versions of those
containers. That no longer compiles, because I changed <regex> to
include <bits/stl_map.h> and <bits/stl_vector.h> instead of <map> and
<vector>, so the debug versions aren't defined, and std::map doesn't
compile. There is also a use of std::stack, which defaults to std::deque
which is the debug deque when _GLIBCXX_DEBUG is defined.
Using std::map, std::vector, and std::deque is probably a mistake, and
we should qualify them with _GLIBCXX_STD_C instead so that the debug
versions aren't used. We do not need the overhead of checking our own
uses of those containers, which should be correct anyway. The exception
is the vector base class of std::match_results, which exposes iterators
to users, so can benefit from debug mode checks for its iterators. For
other accesses to the vector elements, match_results already does its
own checks, so can access the _GLIBCXX_STD_C::vector base class
directly.
Signed-off-by: Jonathan Wakely <jwakely@redhat.com>
libstdc++-v3/ChangeLog:
* include/bits/regex.h (basic_regex::transform_primary): Use
_GLIBCXX_STD_C::vector for local variable.
* include/bits/regex.tcc (__regex_algo_impl): Use reference to
_GLIBCXX_STD_C::vector base class of match_results.
* include/bits/regex_automaton.tcc (_StateSeq:_M_clone): Use
_GLIBCXX_STD_C::map and _GLIBCXX_STD_C::deque for local
variables.
* include/bits/regex_compiler.h (_BracketMatcher): Use
_GLIBCXX_STD_C::vector for data members.
* include/bits/regex_executor.h (_Executor): Likewise.
* include/std/regex [_GLIBCXX_DEBUG]: Include <debug/vector>.
Use std::allocator_traits::is_always_equal to find out if we need to compare
allocator instances on safe container allocator aware move constructor.
libstdc++-v3/ChangeLog:
* include/debug/safe_container.h
(_Safe_container(_Safe_container&&, const _Alloc&, std::true_type)): New.
(_Safe_container(_Safe_container&&, const _Alloc&, std::false_type)): New.
(_Safe_container(_Safe_container&&, const _Alloc&)): Use latters.
I forgot to add -fdump-ipa-inline to options of
testsuite/gcc.dg/ipa/remref-6.c and so the dump scan test were not
PASSing but ended up as UNRESOLVED. Fixing that revealed that the one
of the dumps it was looking for had a double space, so I removed it
too.
gcc/ChangeLog:
2021-08-09 Martin Jambor <mjambor@suse.cz>
PR testsuite/101654
* ipa-prop.c (propagate_controlled_uses): Removed a spurious space.
gcc/testsuite/ChangeLog:
2021-08-09 Martin Jambor <mjambor@suse.cz>
PR testsuite/101654
* gcc.dg/ipa/remref-6.c: Added missing -fdump-ipa-inline option.
Name V2SF logic insns, so expand_simple_binop works with V2SF modes.
2021-08-09 Uroš Bizjak <ubizjak@gmail.com>
gcc/
PR target/101812
* config/i386/mmx.md (<any_logic:code>v2sf3):
Rename from *mmx_<any_logic:code>v2sf3
gcc/testsuite/
PR target/101812
* gcc.target/i386/pr101812.c: New test.
gcc/
* config/nvptx/nvptx.c: Cross-reference parts adapted in
'gcc/omp-oacc-neuter-broadcast.cc'.
* omp-low.c: Likewise.
* omp-oacc-neuter-broadcast.cc: Cross-reference parts adapted from
the above files.
This patch implements worker-partitioning support in the middle end,
by rewriting gimple. The OpenACC execution model requires that code
can run in either "worker single" mode where only a single worker per
gang is active, or "worker partitioned" mode, where multiple workers
per gang are active. This means we need to do something equivalent
to spawning additional workers when transitioning from worker-single
to worker-partitioned mode. However, GPUs typically fix the number of
threads of invoked kernels at launch time, so we need to do something
with the "extra" threads when they are not wanted.
The scheme used is to conditionalise each basic block that executes
in "worker single" mode for worker 0 only. Conditional branches
are handled specially so "idle" (non-0) workers follow along with
worker 0. On transitioning to "worker partitioned" mode, any variables
modified by worker 0 are propagated to the other workers via GPU shared
memory. Special care is taken for routine calls, writes through pointers,
and so forth, as follows:
- There are two types of function calls to consider in worker-single
mode: "normal" calls to maths library routines, etc. are called from
worker 0 only. OpenACC routines may contain worker-partitioned loops
themselves, so are called from all workers, including "idle" ones.
- SSA names set in worker-single mode, but used in worker-partitioned
mode, are copied to shared memory in worker 0. Other workers retrieve
the value from the appropriate shared-memory location after a barrier,
and new phi nodes are introduced at the convergence point to resolve
the worker 0/other worker copies of the value.
- Local scalar variables (on the stack) also need special handling. We
broadcast any variables that are written in the current worker-single
block, and that are read in any worker-partitioned block. (This is
believed to be safe, and is flow-insensitive to ease analysis.)
- Local aggregates (arrays and composites) on the stack are *not*
broadcast. Instead we force gimple stmts modifying elements/fields of
local aggregates into fully-partitioned mode. The RHS of the
assignment is a scalar, and is thus subject to broadcasting as above.
- Writes through pointers may affect any local variable that has
its address taken. We use points-to analysis to determine the set
of potentially-affected variables for a given pointer indirection.
We broadcast any such variable which is used in worker-partitioned
mode, on a per-block basis for any block containing a write through
a pointer.
Some slides about the implementation (from 2018) are available at:
https://jtb20.github.io/gcnworkers.pdf
gcc/
* Makefile.in (OBJS): Add omp-oacc-neuter-broadcast.o.
* doc/tm.texi.in (TARGET_GOACC_CREATE_WORKER_BROADCAST_RECORD):
Add documentation hook.
* doc/tm.texi: Regenerate.
* omp-oacc-neuter-broadcast.cc: New file.
* omp-builtins.def (BUILT_IN_GOACC_BARRIER)
(BUILT_IN_GOACC_SINGLE_START, BUILT_IN_GOACC_SINGLE_COPY_START)
(BUILT_IN_GOACC_SINGLE_COPY_END): New builtins.
* passes.def (pass_omp_oacc_neuter_broadcast): Add pass.
* target.def (goacc.create_worker_broadcast_record): Add target
hook.
* tree-pass.h (make_pass_omp_oacc_neuter_broadcast): Add
prototype.
* config/gcn/gcn-protos.h (gcn_goacc_adjust_propagation_record):
Rename prototype to...
(gcn_goacc_create_worker_broadcast_record): ... this.
* config/gcn/gcn-tree.c (gcn_goacc_adjust_propagation_record): Rename
function to...
(gcn_goacc_create_worker_broadcast_record): ... this.
* config/gcn/gcn.c (TARGET_GOACC_ADJUST_PROPAGATION_RECORD):
Rename to...
(TARGET_GOACC_CREATE_WORKER_BROADCAST_RECORD): ... this.
Co-Authored-By: Nathan Sidwell <nathan@codesourcery.com> (via 'gcc/config/nvptx/nvptx.c' master)
Co-Authored-By: Kwok Cheung Yeung <kcy@codesourcery.com>
Co-Authored-By: Thomas Schwinge <thomas@codesourcery.com>
Loops containing long long shifts fail to vectorize due to the vectorizer
not being able to recognize long long right shifts. This is due to a bug
in the iterator used for the vashr and vlshr patterns in aarch64-simd.md.
2021-08-09 Tejas Belagod <tejas.belagod@arm.com>
gcc/ChangeLog
PR target/101609
* config/aarch64/aarch64-simd.md (vlshr<mode>3, vashr<mode>3): Use
the right iterator.
gcc/testsuite/ChangeLog
* gcc.target/aarch64/vect-shr-reg.c: New testcase.
* gcc.target/aarch64/vect-shr-reg-run.c: Likewise.
Given that it doesn't contain any 'GTY' markers, no 'gcc/gt-omp-offload.h' file
gets generated (and '#include'd anywhere).
Small fix-up for r243673 (Git commit 629b3d75c8)
"Split omp-low into multiple files".
gcc/
* Makefile.in (GTFILES): Remove '$(srcdir)/omp-offload.c'.
Since Tom's PR64707 commit r220037 (Git commit
1506ae0e1e) "Make fopenmp an LTO option" as well
as PR64672 commit r220038 (Git commit a0c88d0629)
"Make fopenacc an LTO option", we're now actually passing
'-fopenacc'/'-fopenmp' to the 'mkoffload's, which will pass these on to the
offload compilers.
gcc/
* builtins.def (DEF_GOACC_BUILTIN, DEF_GOMP_BUILTIN): Don't
consider '-foffload-abi'.
* common.opt (-foffload-abi): Remove 'Var', 'Init'.
* opts.c (common_handle_option) <-foffload-abi> [ACCEL_COMPILER]:
Ignore.
... as that doesn't make sense.
@item Init(@var{value})
The variable specified by the @code{Var} property should be statically
initialized to @var{value}. [...]
gcc/
* optc-gen.awk: Sanity check that 'Init' doesn't appear without
'Var'.
This middle-end patch implements several related improvements to
tree-ssa's conditional (bit) constant propagation pass. The current
code handling ordered comparisons contains the comment "If the
most significant bits are not known we know nothing" which is not
entirely true [this test even prevents this pass understanding these
comparisons always have a zero or one result]. This patch introduces
a new value_mask_to_min_max helper function, that understands the
different semantics of the most significant bit on signed vs.
unsigned values. This allows us to generalize ordered comparisons,
GE_EXPR, GT_EXPR, LE_EXPR and LT_EXPR, where to code is tweaked to
correctly handle the potential equal cases. Then finally support
is added for the related tree codes MIN_EXPR, MAX_EXPR, ABS_EXPR
and ABSU_EXPR.
Regression testing revealed three test cases in the testsuite that
were checking for specific optimizations that are now being performed
earlier than expected. These tests can continue to check their
original transformations by explicitly adding -fno-tree-ccp to their
dg-options (some already specify -fno-ipa-vrp or -fno-tree-forwprop
for the same reason).
2021-08-09 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* tree-ssa-ccp.c (value_mask_to_min_max): Helper function to
determine the upper and lower bounds from a mask-value pair.
(bit_value_unop) [ABS_EXPR, ABSU_EXPR]: Add support for
absolute value and unsigned absolute value expressions.
(bit_value_binop): Initialize *VAL's precision.
[LT_EXPR, LE_EXPR]: Use value_mask_to_min_max to determine
upper and lower bounds of operands. Add LE_EXPR/GE_EXPR
support when the operands are unknown but potentially equal.
[MIN_EXPR, MAX_EXPR]: Support minimum/maximum expressions.
gcc/testsuite/ChangeLog
* gcc.dg/pr68217.c: Add -fno-tree-ccp option.
* gcc.dg/tree-ssa/vrp24.c: Add -fno-tree-ccp option.
* g++.dg/ipa/pure-const-3.C: Add -fno-tree-ccp option.
This patch adds -I$specdir/libgfortran to GFORTRAN_UNDER_TEST, when
set by proc gfortran_init. As the $specdir depends on the multilib
setting, it has to be re-set for a different multilib; hence, we track
whether a previous call to gfortran_init set that var or whether it
was set differently.
gcc/testsuite/
PR libfortran/101305
PR fortran/101660
* lib/gfortran.exp (gfortran_init): Add -I $specdir/libgfortran to
GFORTRAN_UNDER_TEST; update it when set by previous gfortran_init call.
* gfortran.dg/ISO_Fortran_binding_1.c: Use <...> not "..." for
ISO_Fortran_binding.h's #include.
* gfortran.dg/ISO_Fortran_binding_10.c: Likewise.
* gfortran.dg/ISO_Fortran_binding_11.c: Likewise.
* gfortran.dg/ISO_Fortran_binding_12.c: Likewise.
* gfortran.dg/ISO_Fortran_binding_15.c: Likewise.
* gfortran.dg/ISO_Fortran_binding_16.c: Likewise.
* gfortran.dg/ISO_Fortran_binding_17.c: Likewise.
* gfortran.dg/ISO_Fortran_binding_18.c: Likewise.
* gfortran.dg/ISO_Fortran_binding_3.c: Likewise.
* gfortran.dg/ISO_Fortran_binding_5.c: Likewise.
* gfortran.dg/ISO_Fortran_binding_6.c: Likewise.
* gfortran.dg/ISO_Fortran_binding_7.c: Likewise.
* gfortran.dg/ISO_Fortran_binding_8.c: Likewise.
* gfortran.dg/ISO_Fortran_binding_9.c: Likewise.
* gfortran.dg/PR94327.c: Likewise.
* gfortran.dg/PR94331.c: Likewise.
* gfortran.dg/bind_c_array_params_3_aux.c: Likewise.
* gfortran.dg/iso_fortran_binding_uint8_array_driver.c: Likewise.
* gfortran.dg/pr93524.c: Likewise.
Pattern "*extend<SHORT:mode><GPI:mode>2_aarch64" is duplicated
from the corresponding zero_extend pattern, however %<w> needs
to be expanded according to its mode iterator because the smov
instruction is different to umov.
2021-08-09 Bin Cheng <bin.cheng@linux.alibaba.com>
gcc/
* config/aarch64/aarch64.md
(*extend<SHORT:mode><GPI:mode>2_aarch64): Use %<GPI:w>0.
Some scan-assembler tests for SVE code generation were erroneously
split over multiple lines - meaning they became invalid. This patch
gets the tests working again by putting each test on a single line.
The extract_[1234].c tests are corrected to expect that extracted
32-bit values are moved into 'w' registers rather than 'x' registers.
gcc/testsuite/ChangeLog:
2021-08-06 Jonathan Wright <jonathan.wright@arm.com>
* gcc.target/aarch64/sve/dup_lane_1.c: Don't split
scan-assembler tests over multiple lines. Expect 32-bit
result values in 'w' registers.
* gcc.target/aarch64/sve/extract_1.c: Likewise.
* gcc.target/aarch64/sve/extract_2.c: Likewise.
* gcc.target/aarch64/sve/extract_3.c: Likewise.
* gcc.target/aarch64/sve/extract_4.c: Likewise.
Recent refactoring of the arm_neon.h header enabled better code
generation for intrinsics that manipulate vector structures. New
tests were also added to verify the benefit of these changes. It now
transpires that the code generation improvements are observed only on
little-endian systems. This patch restricts the code generation tests
to little-endian targets.
gcc/testsuite/ChangeLog:
2021-08-04 Jonathan Wright <jonathan.wright@arm.com>
* gcc.target/aarch64/vector_structure_intrinsics.c: Restrict
tests to little-endian targets.
A simulator can easily spend more than 10 minutes running
this test-case, and the default timeout is at 5 minutes.
Better allow even slower machines; use 4 as the factor.
Regarding relative runtime numbers (very local; mmixware simulator for
mmix-knuth-mmixware): test01 and test05 finish momentarily; test02 at
about 2 minutes, and test03 about 2m30, but test04 itself runs for
more than 6 minues and so times out.
Not sure if it's better to split up this test, as the excessive
runtime may be unintended, but this seemed simplest.
libstdc++-v3:
* testsuite/std/ranges/iota/max_size_type.cc: Set
dg-timeout-factor to 4.
In gcc.target/arm/pr69245.c, to have a .fpu neon-vfpv4 directive, make
sure code for fn1() is emitted, by removing the static keyword.
Fix a typo in gcc.target/arm/pr69245.c, where \s should be \\s.
2021-08-06 Christophe Lyon <christophe.lyon@foss.st.com>
gcc/testsuite/
PR target/101723
* gcc.target/arm/pr69245.c: Make sure to emit code for fn1, fix
typo.
This removes the cost part of vect_worthwhile_without_simd_p, retaining
only the correctness bits. The reason is that the cost heuristic
do not properly account for SLP plus the check whether "without simd"
applies misfires for AVX512 mask vectors at the moment, leading to
missed vectorizations there.
Any costing decision should take place in the cost modeling, no
single stmt is to disable all vectorization on its own.
2021-08-06 Richard Biener <rguenther@suse.de>
PR tree-optimization/101801
* tree-vectorizer.h (vect_worthwhile_without_simd_p): Rename...
(vect_can_vectorize_without_simd_p): ... to this.
* tree-vect-loop.c (vect_worthwhile_without_simd_p): Rename...
(vect_can_vectorize_without_simd_p): ... to this and fold
in vect_min_worthwhile_factor.
(vect_min_worthwhile_factor): Remove.
(vectorizable_reduction): Adjust and remove the cost part.
* tree-vect-stmts.c (vectorizable_shift): Likewise.
(vectorizable_operation): Likewise.
This patch replaces the use of BUILT_IN_CLRSB with CFN_BUILT_IN_CLRSB
in my recent patch to tree-ssa-phiopt.c. Both of these have identical
values, so there's no change in behavior, but consistent use of the same
enumeration avoids warnings when using clang (or static analysis tools).
2021-08-06 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* tree-ssa-phiopt.c (cond_removal_in_builtin_zero_pattern): Use
CFN_BUILT_IN_CLRSB* instead of BUILT_IN_CLRSB* for consistency.
The build is broken since a3d3e8c362 since it's deleted the ability to pass
vec<> by value and now must be past by reference.
However some language hooks used by AArch64 were not updated and breaks the
build on AArch64. This patch updates these hooks.
gcc/c/ChangeLog:
* c-decl.c (c_simulate_enum_decl): Pass vec<> by pointer.
* c-tree.h (c_simulate_enum_decl): Likewise.
gcc/ChangeLog:
* config/aarch64/aarch64-sve-builtins.cc (register_svpattern,
register_svprfop): Pass vec<> by pointer.
* langhooks-def.h (lhd_simulate_enum_decl): Likewise.
* langhooks.c (lhd_simulate_enum_decl): Likewise.
* langhooks.h (struct lang_hooks_for_types): Likewise.
gcc/cp/ChangeLog:
* cp-objcp-common.h (cxx_simulate_enum_decl): Pass vec<> by pointer.
* decl.c (cxx_simulate_enum_decl): Likewise.
In the patch to add __gcov_info_to_gcda(), the include of <stdint.h> was added
to libgcov-driver.c even if inhibit_libc is defined. It turned out that this
header file is not always available. Remove the include of <stdint.h> and
replace the intptr_t with the compiler provided __INTPTR_TYPE__.
libgcc/
* libgcov-driver.c (#include <stdint.h>): Remove.
(write_topn_counters): Use __INTPTR_TYPE__ instead of intptr_t.
Use __builtin_memcpy to copy vector structures instead of using a
union - or constructing a new opaque structure one vector at a time -
in each of the vst[234][q] and vst1[q]_x[234] bfloat Neon intrinsics
in arm_neon.h.
Add new code generation tests to verify that superfluous move
instructions are not generated for the vst[234]q or vst1q_x[234]
bfloat intrinsics.
gcc/ChangeLog:
2021-07-30 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/arm_neon.h (vst1_bf16_x2): Use
__builtin_memcpy instead of constructing an additional
__builtin_aarch64_simd_oi one vector at a time.
(vst1q_bf16_x2): Likewise.
(vst1_bf16_x3): Use __builtin_memcpy instead of constructing
an additional __builtin_aarch64_simd_ci one vector at a time.
(vst1q_bf16_x3): Likewise.
(vst1_bf16_x4): Use __builtin_memcpy instead of a union.
(vst1q_bf16_x4): Likewise.
(vst2_bf16): Use __builtin_memcpy instead of constructing an
additional __builtin_aarch64_simd_oi one vector at a time.
(vst2q_bf16): Likewise.
(vst3_bf16): Use __builtin_memcpy instead of constructing an
additional __builtin_aarch64_simd_ci mode one vector at a
time.
(vst3q_bf16): Likewise.
(vst4_bf16): Use __builtin_memcpy instead of constructing an
additional __builtin_aarch64_simd_xi one vector at a time.
(vst4q_bf16): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/vector_structure_intrinsics.c: Add new
tests.
Richard Biener
Martin Uecker
H.J. Lu
liuhongt
GCC Administrator
Andrew MacLeod
Jonathan Wakely
François Dumont
Martin Jambor
Pat Haugen
Uros Bizjak
Thomas Schwinge
Julian Brown
Tejas Belagod
Roger Sayle
Tobias Burnus
Bin Cheng
Jonathan Wright
Hongyu Wang
Sergei Trofimovich
Jeff Law
Hans-Peter Nilsson
Ian Lance Taylor
Harald Anlauf
Martin Sebor
Cherry Mui
Christophe Lyon
Tamar Christina
Sebastian Huber