Several recent changes to the gc version of cmd/go improve the
gofrontend support. These changes are partially copies of existing
gofrontend differences, and partially new code. This CL makes the
gofrontend match the upstream code.
The changes included here come from:
https://golang.org/cl/111575https://golang.org/cl/111595https://golang.org/cl/111635https://golang.org/cl/111636
For the record, the following recent gc changes are based on code
already present in the gofrontend repo:
https://golang.org/cl/110915https://golang.org/cl/111615
For the record, a gc change, partially based on earlier gofrontend
work, also with new gc code, was already copied to gofrontend repo in
CL 111099:
https://golang.org/cl/111097
This moves the generated list of standard library packages from
cmd/go/internal/load to go/build.
Reviewed-on: https://go-review.googlesource.com/112475
gotools/:
* Makefile.am (check-go-tool): Don't copy zstdpkglist.go.
* Makefile.in: Rebuild.
From-SVN: r260097
2018-05-09 Tom de Vries <tom@codesourcery.com>
PR libgomp/82901
* oacc-parallel.c (GOACC_declare): Use GOMP_ASYNC_SYNC as async argument
to GOACC_enter_exit_data.
From-SVN: r260085
To satisfy the CopyConstructible requirement a callable object stored in
a std::function must behave the same when copied from a const or
non-const source. If copying a non-const object doesn't produce an
equivalent copy then the behaviour is undefined. But we can make our
std::function more tolerant of such objects by ensuring we always copy
from a const lvalue.
Additionally use an if constexpr statement in the _M_get_pointer
function to avoid unnecessary instantiations in the discarded branch.
* include/bits/std_function.h (_Base_manager::_M_get_pointer):
Use constexpr if in C++17 mode.
(_Base_manager::_M_clone(_Any_data&, const _Any_data&, true_type)):
Copy from const object.
* testsuite/20_util/function/cons/non_copyconstructible.cc: New.
From-SVN: r260080
2018-05-09 Richard Biener <rguenther@suse.de>
* tree-vect-slp.c (vect_bb_slp_scalar_cost): Fill a cost
vector.
(vect_bb_vectorization_profitable_p): Adjust. Compute
actual scalar cost using the cost vector and the add_stmt_cost
machinery.
From-SVN: r260078
The one for the prologue mflr did not have any value set, which means
use the SET that is in the insn pattern. This works fine, except when
some late pass decides to replace the SET_SRC -- this changes the
meaning of the REG_CFA_REGISTER! Such passes should not do these
things, but let's be more explicit here, for extra robustness. It
could be argued that this defaulting is a design misfeature (it does
not save much space either, etc.)
PR rtl-optimization/85645
* config/rs6000/rs6000.c (rs6000_emit_prologue_components): Put a SET
in the REG_CFA_REGISTER note for LR, don't leave it empty.
From-SVN: r260077
In the testcase for PR85645 we do a pretty dumb placement of the
prologue/epilogue for the LR component: we place an epilogue for LR
before a control flow split where one of the branches clobbers LR
eventually, and the other does not. The branch that does clobber it
will need a prologue again some time later. Because saving and
restoring LR is a two step process---it needs to be moved via a GPR---
the backend emits CFI directives so that we get correct unwind
information. But both regcprop and regrename do not properly handle
such CFI directives leading to ICEs.
Now, neither of the two branches needs to have LR restored at all,
because both of the branches end up in an infinite loop.
This patch makes spread_component return a boolean saying if anything
was changed, and if so, it is called again. This obviously is finite
(there is a finite number of basic blocks, each with a finite number
of components, and spread_components can only assign more components
to a block, never less). I also instrumented the code, and on a
bootstrap+regtest spread_components made changes a maximum of two
times. Interestingly though it made changes on two iterations in
a third of the cases it did anything at all!
PR rtl-optimization/85645
* shrink-wrap.c (spread_components): Return a boolean saying if
anything was changed.
(try_shrink_wrapping_separate): Iterate spread_components until
nothing changes anymore.
From-SVN: r260076
We should never change the destination of a REG_CFA_REGISTER, just
like for insns with a REG_CFA_RESTORE, because we need to have the
same control flow information on all branches that join. It is very
doubtful that renaming the scratch registers used for prologue/epilogue
will help anything either.
PR rtl-optimization/85645
* regrename.c (build_def_use): Also kill the chains that include the
destination of a REG_CFA_REGISTER note.
From-SVN: r260075
Changing a SET that has a REG_CFA_REGISTER note is wrong if we are
changing the SET_DEST, or if the REG_CFA_REGISTER has nil as its
argument, and maybe some other cases. It's never really useful to
propagate into such an instruction, so let's just bail whenever we
see such a note.
PR rtl-optimization/85645
* regcprop.c (copyprop_hardreg_forward_1): Don't propagate into an
insn that has a REG_CFA_REGISTER note.
From-SVN: r260074
We build up the input to IFN_STORE_LANES one vector at a time.
In RTL, each of these vector assignments becomes a write to
subregs of the form (subreg:VEC (reg:AGGR R)), where R is the
eventual input to the store lanes instruction. The problem is
that RTL isn't very good at tracking liveness when things are
initialised piecemeal by subregs, so R tends to end up being
live on all paths from the entry block to the store. This in
turn leads to unnecessary spilling around calls, as well as to
excess register pressure in vector loops.
This patch adds gimple clobbers to indicate the liveness of the
IFN_STORE_LANES variable and makes sure that gimple clobbers are
expanded to rtl clobbers where useful. For consistency it also
uses clobbers to mark the point at which an IFN_LOAD_LANES
variable is no longer needed.
2018-05-08 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* cfgexpand.c (expand_clobber): New function.
(expand_gimple_stmt_1): Use it.
* tree-vect-stmts.c (vect_clobber_variable): New function,
split out from...
(vectorizable_simd_clone_call): ...here.
(vectorizable_store): Emit a clobber either side of an
IFN_STORE_LANES sequence.
(vectorizable_load): Emit a clobber after an IFN_LOAD_LANES sequence.
gcc/testsuite/
* gcc.target/aarch64/store_lane_spill_1.c: New test.
* gcc.target/aarch64/sve/store_lane_spill_1.c: Likewise.
From-SVN: r260073
PR rtl-optimization/85638
* bb-reorder.c: Include common/common-target.h.
(create_forwarder_block): New function extracted from...
(fix_up_crossing_landing_pad): ...here. Rename into...
(dw2_fix_up_crossing_landing_pad): ...this.
(sjlj_fix_up_crossing_landing_pad): New function.
(find_rarely_executed_basic_blocks_and_crossing_edges): In SJLJ mode,
call sjlj_fix_up_crossing_landing_pad if there are incoming EH edges
from both partitions and exit the loop after one iteration.
From-SVN: r260070
* pt.c (for_each_template_parm_r): Handle DECLTYPE_TYPE. Clear
*walk_subtrees whether or not we walked into the operand.
(type_uses_auto): Only look at deduced contexts.
From-SVN: r260066
2018-05-08 Kelvin Nilsen <kelvin@gcc.gnu.org>
Revert:
* doc/extend.texi (PowerPC Built-in Functions): Rename this
subsection.
(Basic PowerPC Built-in Functions): The new name of the
subsection previously known as "PowerPC Built-in Functions".
(Basic PowerPC Built-in Functions Available on all Configurations):
New subsubsection.
(Basic PowerPC Built-in Functions Available on ISA 2.05): New
subsubsection.
(Basic PowerPC Built-in Functions Available on ISA 2.06): New
subsubsection.
(Basic PowerPC Built-in Functions Available on ISA 2.07): New
subsubsection.
(Basic PowerPC Built-in Functions Available on ISA 3.0): New
subsubsection.
From-SVN: r260065
gcc/ChangeLog:
2018-05-08 Kelvin Nilsen <kelvin@gcc.gnu.org>
* doc/extend.texi (PowerPC Built-in Functions): Rename this
subsection.
(Basic PowerPC Built-in Functions): The new name of the
subsection previously known as "PowerPC Built-in Functions".
(Basic PowerPC Built-in Functions Available on all Configurations):
New subsubsection.
(Basic PowerPC Built-in Functions Available on ISA 2.05): New
subsubsection.
(Basic PowerPC Built-in Functions Available on ISA 2.06): New
subsubsection.
(Basic PowerPC Built-in Functions Available on ISA 2.07): New
subsubsection.
(Basic PowerPC Built-in Functions Available on ISA 3.0): New
subsubsection.
From-SVN: r260048
PR target/85683
* config/i386/i386.md: Add peepholes for mem {+,-,&,|,^}= x; mem != 0
after cmpelim optimization.
* gcc.target/i386/pr49095.c: Add -masm=att to dg-options. Add
scan-assembler-times checking that except for [fh]*xor other functions
don't use any load instructions.
From-SVN: r260045
Restore the behaviour in GCC 8 and earlier where _GLIBCXX_USE_FLOAT128
is not defined when configure detects support is missing. This avoids
having three states where the macro is either 1, 0, or undefined.
PR libstdc++/85672
* include/Makefile.am [!ENABLE_FLOAT128]: Change c++config.h entry
to #undef _GLIBCXX_USE_FLOAT128 instead of defining it to zero.
* include/Makefile.in: Regenerate.
* include/bits/c++config (_GLIBCXX_USE_FLOAT128): Move definition
within conditional block.
From-SVN: r260043
PR target/85572
* config/i386/i386.c (ix86_expand_sse2_abs): Handle E_V2DImode and
E_V4DImode.
* config/i386/sse.md (abs<mode>2): Use VI_AVX2 iterator instead of
VI1248_AVX512VL_AVX512BW. Handle V2DImode and V4DImode if not
TARGET_AVX512VL using ix86_expand_sse2_abs. Formatting fixes.
* g++.dg/other/sse2-pr85572-1.C: New test.
* g++.dg/other/sse2-pr85572-2.C: New test.
* g++.dg/other/sse4-pr85572-1.C: New test.
* g++.dg/other/avx2-pr85572-1.C: New test.
From-SVN: r260041
There are a number of places in parsecpu.awk where I've managed to get
the operator precedence between ! and 'in' incorrect (! binds more
tightly). In most cases this just makes a consistency test
ineffective, but in a few cases it means we fail to correctly diagnose
errors by the user (for example, when passing an invalid cpu or
architecture name to configure. This patch fixes all the cases I
could find, based on searching for all uses of the two operators in
the same expression. The tweak to the API of check_fpu is to bring it
into line with the other check functions - it now returns the result
rather than printing it directly. The caller now does the printing,
in the same way that the chkarch and chkcpu commands do.
PR target/85658
* config/arm/parsecpu.awk (check_cpu): Fix operator precedence.
(check_arch): Likewise.
(check_fpu): Return the result rather than printing it.
(end arch): Fix operator precedence.
(end cpu): Likewise.
(END): Print the result from check_fpu.
From-SVN: r260032
This patch adds SVE patterns that combine a PTRUE-predicated
comparison with a separate AND. The main benefit is for
optimising ANDs with the loop predicate, as in the testcase.
However, one of the potential drawbacks is that it triggers
even for cases in which two naturally-parallel comparisons
are ANDed together. Whether that's a win or a less will
depend on the schedule, but it has the potential to be a win
more often than a loss.
The combine patterns are undeniably ugly. One way of getting
around them would be to allow 1->1 "splits" when combining
2 instructions, as well as 1->2 splits when combining more
than 2 instructions (although that wouldn't really be a split).
Another would be to have a way of defining target-specific
rtx simplifications. branches/ARM/sve-branch has a prototype
implementation of that, but it would need some clean-up before being
ready to submit. It would also be good to make it closer to the
match.pd style.
Until then, I think what the combine patterns are doing is the
"correct" implementation given the current infrastructure.
2018-05-08 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* config/aarch64/aarch64-sve.md (*pred_cmp<cmp_op><mode>_combine)
(*pred_cmp<cmp_op><mode>, *fcm<cmp_op><mode>_and_combine)
(*fcmuo<mode>_and_combine, *fcm<cmp_op><mode>_and)
(*fcmuo<mode>_and): New patterns.
gcc/testsuite/
* gcc.target/aarch64/sve/vcond_6.c: Do not expect any ANDs.
XFAIL the BIC test.
* gcc.target/aarch64/sve/vcond_7.c: New test.
* gcc.target/aarch64/sve/vcond_7_run.c: Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r260031
This patch rewrites the SVE comparison handling so that it uses
UNSPEC_MERGE_PTRUE for comparisons that are known to be predicated
on a PTRUE, for consistency with other patterns. Specific unspecs
are then only needed for truly predicated floating-point comparisons,
such as those used in the expansion of UNEQ for flag_trapping_math.
The patch also makes sure that the comparison expanders attach
a REG_EQUAL note to instructions that use UNSPEC_MERGE_PTRUE,
so passes can use that as an alternative to the unspec pattern.
(This happens automatically for optabs. The problem was that
this code emits instruction patterns directly.)
No specific benefit on its own, but it lays the groundwork for
the next patch.
2018-05-08 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* config/aarch64/iterators.md (UNSPEC_COND_LO, UNSPEC_COND_LS)
(UNSPEC_COND_HI, UNSPEC_COND_HS, UNSPEC_COND_UO): Delete.
(SVE_INT_CMP, SVE_FP_CMP): New code iterators.
(cmp_op, sve_imm_con): New code attributes.
(SVE_COND_INT_CMP, imm_con): Delete.
(cmp_op): Remove above unspecs from int attribute.
* config/aarch64/aarch64-sve.md (*vec_cmp<cmp_op>_<mode>): Rename
to...
(*cmp<cmp_op><mode>): ...this. Use UNSPEC_MERGE_PTRUE instead of
comparison-specific unspecs.
(*vec_cmp<cmp_op>_<mode>_ptest): Rename to...
(*cmp<cmp_op><mode>_ptest): ...this and adjust likewise.
(*vec_cmp<cmp_op>_<mode>_cc): Rename to...
(*cmp<cmp_op><mode>_cc): ...this and adjust likewise.
(*vec_fcm<cmp_op><mode>): Rename to...
(*fcm<cmp_op><mode>): ...this and adjust likewise.
(*vec_fcmuo<mode>): Rename to...
(*fcmuo<mode>): ...this and adjust likewise.
(*pred_fcm<cmp_op><mode>): New pattern.
* config/aarch64/aarch64.c (aarch64_emit_unop, aarch64_emit_binop)
(aarch64_emit_sve_ptrue_op, aarch64_emit_sve_ptrue_op_cc): New
functions.
(aarch64_unspec_cond_code): Remove handling of LTU, GTU, LEU, GEU
and UNORDERED.
(aarch64_gen_unspec_cond, aarch64_emit_unspec_cond): Delete.
(aarch64_emit_sve_predicated_cond): New function.
(aarch64_expand_sve_vec_cmp_int): Use aarch64_emit_sve_ptrue_op_cc.
(aarch64_emit_unspec_cond_or): Replace with...
(aarch64_emit_sve_or_conds): ...this new function. Use
aarch64_emit_sve_ptrue_op for the individual comparisons and
aarch64_emit_binop to OR them together.
(aarch64_emit_inverted_unspec_cond): Replace with...
(aarch64_emit_sve_inverted_cond): ...this new function. Use
aarch64_emit_sve_ptrue_op for the comparison and
aarch64_emit_unop to invert the result.
(aarch64_expand_sve_vec_cmp_float): Update after the above
changes. Use aarch64_emit_sve_ptrue_op for native comparisons.
From-SVN: r260029
sve/vcond_6.c was effectively testing a three-input logical operation,
since the result of BINOP needed to be ANDed with the loop predicate
before loading src[i]. This patch makes it really test a binary
operation instead. A later patch will add (and optimise) the
three-operand case.
2018-05-08 Richard Sandiford <richard.sandiford@linaro.org>
gcc/testsuite/
* gcc.target/aarch64/sve/vcond_6.c (LOOP): Unconditionally
load from src[i].
From-SVN: r260028
GCC Administrator
Ian Lance Taylor
Jim Wilson
François Dumont
Paolo Carlini
Carl Love
Paolo Carlini
Tom de Vries
Joshua Watt
Andreas Schwab
Jonathan Wakely
Richard Biener
Segher Boessenkool
Richard Sandiford
Eric Botcazou
Jason Merrill
Kelvin Nilsen
Joseph Myers
Marek Polacek
Uros Bizjak
Jakub Jelinek
Olga Makhotina
Richard Earnshaw